2017 12th IEEE International Symposium on Industrial Embedded Systems (SIES)最新文献_第2页

A greedy heuristic for distributing hard real-time applications on an IMA architecture 在IMA架构上分发硬实时应用程序的贪婪启发式算法

2017 12th IEEE International Symposium on Industrial Embedded Systems (SIES) Pub Date : 2017-06-01 DOI: 10.1109/SIES.2017.7993390

Emilie Deroche, Jean-Luc Scharbarg, C. Fraboul

{"title":"A greedy heuristic for distributing hard real-time applications on an IMA architecture","authors":"Emilie Deroche, Jean-Luc Scharbarg, C. Fraboul","doi":"10.1109/SIES.2017.7993390","DOIUrl":"https://doi.org/10.1109/SIES.2017.7993390","url":null,"abstract":"Current avionics architectures use complex processors, which are shared by many avionics applications according Integrated Modular Avionics (IMA) concepts. Using less complex processors on small aircraft such as helicopters leads to a distributed IMA architecture. Thus the set of partitions has to be distributed on the set of available processors. This distribution has to deal with both schedulability constraints on each processor and end-to-end latency constraints for chains of communicating partitions. Several mapping approaches exist for various applicative contexts. An approach has been proposed in the context of avionics. It implements an exhaustive analysis of all possible mappings. Time needed to perform this exhaustive analysis is drastically limited by incrementally mapping avionics functions and checking both scheduling and end-to-end constraints at each step. This approach is able to map small avionics application. However, it doesn’t scale well, mainly because the scheduling space quickly explodes. In this paper, we integrate a greedy heuristic in the approach, in order to limit the scheduling space. We show that the resulting approach scales much better and gives mapping results which are close to those of the exhaustive approach.","PeriodicalId":262681,"journal":{"name":"2017 12th IEEE International Symposium on Industrial Embedded Systems (SIES)","volume":"517 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2017-06-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133565474","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 3

Generation of simulink monitors for control applications from formal requirements 根据正式要求为控制应用程序生成simulink监视器

2017 12th IEEE International Symposium on Industrial Embedded Systems (SIES) Pub Date : 2017-06-01 DOI: 10.1109/SIES.2017.7993389

Alessio Balsini, M. Natale, M. Celia, V. Tsachouridis

引用次数: 10

Architecture exploration for distributed embedded systems: a gap analysis in automotive domain 分布式嵌入式系统的架构探索:汽车领域的差距分析

2017 12th IEEE International Symposium on Industrial Embedded Systems (SIES) Pub Date : 2017-06-01 DOI: 10.1109/SIES.2017.7993377

Xinhai Zhang, N. Mohan, Martin Törngren, J. Axelsson, De-Jiu Chen

引用次数: 8

Probabilistic schedulability tests for uniprocessor fixed-priority scheduling under soft errors 软错误下单处理器固定优先级调度的概率可调度性测试

2017 12th IEEE International Symposium on Industrial Embedded Systems (SIES) Pub Date : 2017-06-01 DOI: 10.1109/SIES.2017.7993392

Kuan-Hsun Chen, Jian-Jia Chen

{"title":"Probabilistic schedulability tests for uniprocessor fixed-priority scheduling under soft errors","authors":"Kuan-Hsun Chen, Jian-Jia Chen","doi":"10.1109/SIES.2017.7993392","DOIUrl":"https://doi.org/10.1109/SIES.2017.7993392","url":null,"abstract":"Due to rising integrations, low voltage operations, and environmental influences such as electromagnetic interference and radiation, transient faults may cause soft errors and corrupt the execution state. Such soft errors can be recovered by applying fault-tolerant techniques. Therefore, the execution time of a job of a sporadic/periodic task may differ, depending upon the occurrence of soft errors and the applied error detection and recovery mechanisms. We model a periodic/sporadic real-time task under such a scenario by using two different worst-case execution times (WCETs), in which one is with the occurrence of soft errors and another is not. Based on a probabilistic soft-error model, the WCETs are hence with different probabilities. In this paper, we present efficient probabilistic schedulability tests that can be applied to verify the schedulability based on probabilistic arguments under fixed-priority scheduling on a uniprocessor system. We demonstrate how the Chernoff bounds can be used to calculate the task workloads based on their probabilistic WCETs. In addition, we further consider how to calculate the probability of `-consecutive deadline misses of a task. The pessimism and the efficiency of our approaches are evaluated against the tighter and approximated convolution-based approaches, by running extensive evaluations under different soft-error rates. The evaluation results show that our approaches are effective to derive the probability of deadline misses and efficient with respect to the needed calculation time.","PeriodicalId":262681,"journal":{"name":"2017 12th IEEE International Symposium on Industrial Embedded Systems (SIES)","volume":"7 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2017-06-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123710870","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 24

Power and performance aware electronic system level design 功耗和性能敏感的电子系统级设计

2017 12th IEEE International Symposium on Industrial Embedded Systems (SIES) Pub Date : 2017-06-01 DOI: 10.1109/SIES.2017.7993374

Amal Ben Ameur, Didier Martinot, P. Guitton-Ouhamou, V. Frascolla, F. Verdier, M. Auguin

引用次数: 7

HLshield: a reliability enhancement framework for high-level synthesis HLshield:用于高级合成的可靠性增强框架

2017 12th IEEE International Symposium on Industrial Embedded Systems (SIES) Pub Date : 2017-06-01 DOI: 10.1109/SIES.2017.7993378

Christian Fibich, M. Horauer, R. Obermaisser

{"title":"HLshield: a reliability enhancement framework for high-level synthesis","authors":"Christian Fibich, M. Horauer, R. Obermaisser","doi":"10.1109/SIES.2017.7993378","DOIUrl":"https://doi.org/10.1109/SIES.2017.7993378","url":null,"abstract":"High-Level Synthesis (HLS) is more and more becoming an important part of the digital logic design flow. Rapid development of hardware offloading designs implemented in FPGA accelerators or in the programmable logic area of modern SoC FPGAs is facilitated by the ability of today’s HLS tools to generate logic from generic programming languages such as C and C++. When such accelerators are used in applications requiring high reliability, such as safety-critical systems, the designer has to consider the possibility of soft errors occurring during run time. In this paper, the HLShield framework is proposed that aims at integrating approaches from previous work and novel techniques into the HLS process to eliminate the need to add fault tolerance functionality to the generated Hardware Description Language (HDL) code by hand. The proposed framework provides means for profiling the reliability of the original high-level source code. It allows to direct the generation of reliability-enhanced hardware descriptions by specifying the desired protection methods using source code annotations. Means for evaluating the reliability of the selected solution are also included in the framework. A proof of concept implementation for the proposed framework is presented which is able to protect registers and memories corresponding to selected variables in the original high-level source code with errorcorrecting codes. This process is supported by a profiling tool that suggests especially critical variables. The achieved reliability improvements were evaluated using fault injection experiments carried out on multiple protection levels of three use case designs. Evaluations showed that significant gains in reliability can be made when using the presented profiling approach to protect storage elements in the generated hardware.","PeriodicalId":262681,"journal":{"name":"2017 12th IEEE International Symposium on Industrial Embedded Systems (SIES)","volume":"112 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2017-06-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130831645","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 3

Binary protection framework for embedded systems 嵌入式系统二进制保护框架

2017 12th IEEE International Symposium on Industrial Embedded Systems (SIES) Pub Date : 2017-06-01 DOI: 10.1109/SIES.2017.7993401

Florian Gerstmayer, Jürgen Hausladen, M. Kramer, M. Horauer

{"title":"Binary protection framework for embedded systems","authors":"Florian Gerstmayer, Jürgen Hausladen, M. Kramer, M. Horauer","doi":"10.1109/SIES.2017.7993401","DOIUrl":"https://doi.org/10.1109/SIES.2017.7993401","url":null,"abstract":"Embedded systems empower many products and are used in a variety of applications ranging from smart homes to modern cars. Respective technologies enable new functional features and at the same time improve also non-functional aspects like environmental efficiency. Especially, their inter-connection and coupling with existing networks – in particular to the Internet – allow for an unprecedented boost. However, at the same time security concerns emerge since respective security breaches may have dire consequences ranging from malfunctions, theft, tampering of intellectual property up to threats of safety. This paper presents a generic protection framework for binary file images. The focus of the framework is on hindering reverse engineering and to ensure integrity of embedded systems software. It is designed to be applied in a post-development stage and can be used to add/improve security features of existing products in a number of ways. The concept, a proof-of-concept implementation as well as several key features, such as an in-memory library, a userland-exec implementation, and antidebugging & anti-tampering mechanisms are elaborated.","PeriodicalId":262681,"journal":{"name":"2017 12th IEEE International Symposium on Industrial Embedded Systems (SIES)","volume":"32 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2017-06-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116140839","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 2

Probabilistic model of AFDX frames reception for end system backlog assessment 用于终端系统积压评估的AFDX帧接收概率模型

2017 12th IEEE International Symposium on Industrial Embedded Systems (SIES) Pub Date : 2017-06-01 DOI: 10.1109/SIES.2017.7993400

Yohan Baga, Morgane Richaud, Ghaffari Fakhreddine, E. Zante, D. Declercq, Michael Nahmiyace

{"title":"Probabilistic model of AFDX frames reception for end system backlog assessment","authors":"Yohan Baga, Morgane Richaud, Ghaffari Fakhreddine, E. Zante, D. Declercq, Michael Nahmiyace","doi":"10.1109/SIES.2017.7993400","DOIUrl":"https://doi.org/10.1109/SIES.2017.7993400","url":null,"abstract":"The Avionics Full-Duplex Switched Ethernet (AFDX) network has established itself as a reference in aeronautical embedded communications to comply with the growth of bandwidth needs and the reliability requirements. Its determinism property imposes that AFDX frames have to transit through the network in a limited amount of time. Due to potential delays in the processing frames at a reception End-System, the frames have to be stored in a reception buffer. Generally, the buffer is dimensioned enough large to avoid prohibitive frame losses, but it results a waste of memory resources. The buffer dimensioning issue requires an analysis of the reception flow to determine the worst frame backlog. As the frame backlog is maximal when a sequence of back-to-back frames is received by the ES, the key point is to estimate the occurrences of such SBFs on a representative sample of received frames. In this paper, we address this issue using a probabilistic model based on local Gaussian distributions, and we propose results for a range of typical configuration tables of the reception End-System.","PeriodicalId":262681,"journal":{"name":"2017 12th IEEE International Symposium on Industrial Embedded Systems (SIES)","volume":"24 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2017-06-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126039822","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 5

SMT-based architecture modelling for safety assessment 基于smt的安全评估体系结构建模

2017 12th IEEE International Symposium on Industrial Embedded Systems (SIES) Pub Date : 2017-06-01 DOI: 10.1109/SIES.2017.7993379

Kevin Delmas, R. Delmas, C. Pagetti

引用次数: 3

Keynote talks 专题演讲

2017 12th IEEE International Symposium on Industrial Embedded Systems (SIES) Pub Date : 2017-06-01 DOI: 10.1109/SIES.2017.7993396

A. Rossignol

引用次数: 1