SMT-based architecture modelling for safety assessment

Safety is one of the main guidelines for critical systems design. Designers are in charge of developing architectures that comply with the safety requirements. Thus they must ensure that qualitative safety indicators such as the minimal size of failures scenario leading to a failure condition fc and quantitative indicators such as the probability to reach fc after a certain time interval, are kept below a given threshold. In this paper, we propose efficient minimal cutsets computation and analysis methods fully based on state-of-the-art Satisfiability Modulo Theory (SMT) and Boolean satisfiability (SAT) solvers. The efficiency of minimal cutsets computation, which does not rely on any intermediate model of the system such as fault trees is compared to classic formal analysis methods.