2017 12th IEEE International Symposium on Industrial Embedded Systems (SIES)最新文献

{"title":"On uses of extreme value theory fit for industrial-quality WCET analysis","authors":"Suzana Milutinovic, E. Mezzetti, J. Abella, T. Vardanega, F. Cazorla","doi":"10.1109/SIES.2017.7993402","DOIUrl":"https://doi.org/10.1109/SIES.2017.7993402","url":null,"abstract":"Over the last few years, considerable interest has arisen in measurement-based probabilistic timing analysis. The term MBPTA has been used to indistinctly refer to a variety of different applications of Extreme Value Theory (EVT) to the timing analysis problem. The successful application of MBPTA techniques to a score of case studies has not fully dispelled the concerns that industrial stakeholders had with the quality of the computed bounds, hence ultimately with their industrial viability. Placing focus on the MBPTA methods and techniques developed in the PROARTIS and PROXIMA projects, collectively referred to as proMBPTA, we discuss the main misconceptions and pitfalls that can prevent a sound application of EVT-based WCET analysis. Using a combination of arguments and support examples, we show that proMBPTA is a rigorous process, fully amenable to sound and sustainable industrial use.","PeriodicalId":262681,"journal":{"name":"2017 12th IEEE International Symposium on Industrial Embedded Systems (SIES)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2017-07-31","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131314256","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Modelling bus contention during system early design stages","authors":"David Trilla, Carles Hernández, J. Abella, F. Cazorla","doi":"10.1109/SIES.2017.7993393","DOIUrl":"https://doi.org/10.1109/SIES.2017.7993393","url":null,"abstract":"Reliably upperbounding contention in multicore shared resources is of prominent importance in the early design phases of critical real-time systems to properly allocate time budgets to applications. However, during early stages applications are not yet consolidated and IP constraints may prevent sharing them across providers, challenging the estimation of contention bounds. In this paper, we propose a model to estimate the increase in applications’ execution time due to on-chip bus sharing when they simultaneously execute in a multicore. The model works with information derived from the execution of each application in isolation, hence, without the need to actually run applications simultaneously. The model improves inaccuracy with respect to the existing model, and tends to over-estimate. The latter, is very important to prevent that, during late design stages, applications miss their deadline when consolidated into the same multicore, causing costly system redesign.","PeriodicalId":262681,"journal":{"name":"2017 12th IEEE International Symposium on Industrial Embedded Systems (SIES)","volume":"14 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2017-07-31","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129114619","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"FPGA-based digital tunable wireless transceiver for the TETRA-TETRAPOL bands","authors":"N. Harb, C. Valderrama, J. Pisane","doi":"10.1109/SIES.2017.7993398","DOIUrl":"https://doi.org/10.1109/SIES.2017.7993398","url":null,"abstract":"Wireless digital repeaters are used to amplify cellular signals in different scenarios and environments using several frequency bands and radio links. The market for such repeaters varies between the demand for a specific scenario and a specific frequency radio band. In this work we present a dynamic and all purpose FPGA based repeater implemented in an actual industrial product. We present the FPGA based digital repeater customised for usage in different scenarios, frequency bands and number of channels. The procedure from developing an emulator to acquire test data and potential processing modules through the FPGA based implementation and industrialisation is the core of this work. We show that the main advantage of our solution is reconfigurability not just in filter coefficients, number of channels and taps but also in adding new functional blocks and using different configurations thanks to the use of FPGAs.","PeriodicalId":262681,"journal":{"name":"2017 12th IEEE International Symposium on Industrial Embedded Systems (SIES)","volume":"92 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2017-06-14","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124598238","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Towards virtual prototyping of synchronous real-time systems on noc-based MPSoCs","authors":"Razi Seyyedi, M. T. Mohammadat, Maher Fakih, Kim Grüttner, Johnny Öberg, Duncan Graham","doi":"10.1109/SIES.2017.7993375","DOIUrl":"https://doi.org/10.1109/SIES.2017.7993375","url":null,"abstract":"NoC-based designs provide a scalable and flexible communication solution for the rising number of processing cores on a single chip. To master the complexity of the software design in such a NoC-based multi-core architecture, advanced incremental integration testing solutions are required. This work presents a virtual platform based software testing and debugging approach for a synchronous application model on a NoC-based designs provide a scalable and flexible communication solution for the rising number of processing cores on a single chip. To master the complexity of the software design in such a NoC-based multi-core architecture, advanced incremental integration testing solutions are required. This work presents a virtual platform based software testing and debugging approach for a synchronous application model on a 2x2 NoC-based MPSoC. We propose a development approach and a test environment that exploits the time approximation within Imperas OVP instruction accurate simulator and a functional model of the Nostrum NoC, for both software instructions and hardware clock cycles at larger time stamps called Quantum that does not sacrifice functional correctness. The functional testing environment runs the target software without running it on the real hardware platform. With the help of Nostrum NoC we can support a synchronous system execution that is reasonably fast and precise with respect to a global synchronization signal, called HeartBeat. As work in progress, this work also discusses several possible timing refinement and their possible implication on the simulation semantics and performance and how it is tackled in the future work. NoC-based MPSoC. We propose a development approach and a test environment that exploits the time approximation within Imperas OVP instruction accurate simulator and a functional model of the Nostrum NoC, for both software instructions and hardware clock cycles at larger time stamps called Quantum that does not sacrifice functional correctness. The functional testing environment runs the target software without running it on the real hardware platform. With the help of Nostrum NoC we can support a synchronous system execution that is reasonably fast and precise with respect to a global synchronization signal, called HeartBeat. As work in progress, this work also discusses several possible timing refinement and their possible implication on the simulation semantics and performance and how it is tackled in the future work.","PeriodicalId":262681,"journal":{"name":"2017 12th IEEE International Symposium on Industrial Embedded Systems (SIES)","volume":"511 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2017-06-14","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115344780","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"More accurate complex multiplication for embedded processors","authors":"C. Jeannerod, Christophe Monat, Laurent Thévenoux","doi":"10.1109/SIES.2017.7993403","DOIUrl":"https://doi.org/10.1109/SIES.2017.7993403","url":null,"abstract":"This paper presents some work in progress on the development of fast and accurate support for complex floatingpoint arithmetic on embedded processors. Focusing on the case of multiplication, we describe algorithms and implementations for computing both the real and imaginary parts with high relative accuracy. We show that, in practice, such accuracy guarantees can be achieved with reasonable overhead compared with conventional algorithms (which are those offered by current implementations and for which the real or imaginary part of a product can have no correct digit at all). For example, the average execution-time overheads when computing an FFT on the ARM Cortex-A53 and -A57 processors range from 1.04x to 1.17x only, while arithmetic costs suggest overheads from 1.5x to 1.8x.","PeriodicalId":262681,"journal":{"name":"2017 12th IEEE International Symposium on Industrial Embedded Systems (SIES)","volume":"98 1-3","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2017-06-14","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"120907275","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Adaptive video-based algorithm for accident detection on highways","authors":"Boutheina Maaloul, A. Taleb-Ahmed, S. Niar, N. Harb, C. Valderrama","doi":"10.1109/SIES.2017.7993382","DOIUrl":"https://doi.org/10.1109/SIES.2017.7993382","url":null,"abstract":"For the past few decades, automatic accident detection, especially using video analysis, has become a very important subject. It is important not only for traffic management but also, for Intelligent Transportation Systems (ITS) through its contribution to avoid the escalation of accidents especially on highways. In this paper a novel vision-based road accident detection algorithm on highways and expressways is proposed. This algorithm is based on an adaptive traffic motion flow modeling technique, using Farneback Optical Flow for motions detection and a statistic heuristic method for accident detection. The algorithm was applied on a set of collected videos of traffic and accidents on highways. The results prove the efficiency and practicability of the proposed algorithm using only 240 frames for traffic motion modeling. This method avoids to utilization of a large database while adequate and common accidents videos benchmarks do not exist.","PeriodicalId":262681,"journal":{"name":"2017 12th IEEE International Symposium on Industrial Embedded Systems (SIES)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2017-06-14","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130913685","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Soft real-time smartphone ECG processing","authors":"G. Tsamis, M. Grammatikakis, A. Papagrigoriou, P. Petrakis, Voula Piperaki, A. Mouzakitis, M. Coppola","doi":"10.1109/SIES.2017.7993395","DOIUrl":"https://doi.org/10.1109/SIES.2017.7993395","url":null,"abstract":"Mobile health monitoring technology has the potential to bring a doctor’s office to the patient’s smartphone. In this context, we consider an end-to-end soft real-time out-ofhospital use-case that concerns transmission of patient ECG data from ST BodyGateway pulse sensor via an Android device (Patient App) to a Cloud server for ECG analysis and annotation and then to another Android device (Doctor App) for visualization. Using a prototype featuring ARMv7 technology (two Odroid-XU4s for Patient and Doctor App and one Zedboard FPGA board for server), we evaluate real-time performance and security overheads for supporting confidentiality, integrity and patient anonymity.","PeriodicalId":262681,"journal":{"name":"2017 12th IEEE International Symposium on Industrial Embedded Systems (SIES)","volume":"19 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2017-06-14","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123830641","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"On the tailoring of CAST-32A certification guidance to real COTS multicore architectures","authors":"Irune Agirre, J. Abella, M. Azkarate-askasua, F. Cazorla","doi":"10.1109/SIES.2017.7993376","DOIUrl":"https://doi.org/10.1109/SIES.2017.7993376","url":null,"abstract":"The use of Commercial Off-The-Shelf (COTS) multicores in real-time industry is on the rise due to multicores' potential performance increase and energy reduction. Yet, the unpredictable impact on timing of contention in shared hardware resources challenges certification. Furthermore, most safety certification standards target single-core architectures and do not provide explicit guidance for multicore processors. Recently, however, CAST-32A has been presented providing guidance for software planning, development and verification in multicores. In this paper, from a theoretical level, we provide a detailed review of CAST-32A objectives and the difficulty of reaching them under current COTS multicore design trends; at experimental level, we assess the difficulties of the application of CAST-32A to a real multicore processor, the NXP P4080.","PeriodicalId":262681,"journal":{"name":"2017 12th IEEE International Symposium on Industrial Embedded Systems (SIES)","volume":"31 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2017-06-14","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"134065898","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Model-based deployment generation for safety-critical avionics systems","authors":"G. Igna, L. Dieudonné, S. Voss, B. Schätz","doi":"10.1109/SIES.2017.7993394","DOIUrl":"https://doi.org/10.1109/SIES.2017.7993394","url":null,"abstract":"To reduce the growth in size, weight and power of avionic electronic systems, the avionics industry tends to integrate more and more functions on less electronic computing units. Particularly, the use of multicore processors seems ineluctable in this domain. These changes, however, bring new challenges regarding, among others, methods and tools to proof safety and timing requirements for new platform architectures. One complex task to be solved during the design phase is the so-called deployment problem, which analyzes possible mappings between software applications and hardware execution units. Without the help of dedicated tools and due to the large number of constraints avionics systems need to fulfill, this problem becomes intractable. In this paper, we employ a model-based development tool, called AutoFOCUS 3, to generate deployment solutions for an industrial case study based on a flight control system with strict requirements regarding safety, timing, storage and communication aspects. We have also customized AutoFOCUS 3 to seek optimized deployment solutions with respect to the number of cores and other hardware resources.","PeriodicalId":262681,"journal":{"name":"2017 12th IEEE International Symposium on Industrial Embedded Systems (SIES)","volume":"132 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2017-06-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127090754","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Minimizing the aperiodic responsiveness in energy harvesting devices","authors":"Rola El Osta, M. Chetto, Hussein El Ghor","doi":"10.1109/SIES.2017.7993386","DOIUrl":"https://doi.org/10.1109/SIES.2017.7993386","url":null,"abstract":"This paper presents a new aperiodic request server in real-time energy harvesting system. This server handles hard periodic tasks and soft aperiodic tasks, using ED-H in order to schedule periodic tasks. The main principle of the server is to minimize response times of aperiodic tasks without compromising the schedulability of periodic tasks. The server, known as SSP (Slack stealing with Energy Preserving), enhances the response time offered by the Slack stealing approach, because of idle times and energy surplus. Finally, performance evaluation is made by comparing the server with two background servers.","PeriodicalId":262681,"journal":{"name":"2017 12th IEEE International Symposium on Industrial Embedded Systems (SIES)","volume":"123 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2017-06-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130909183","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}