Power and performance aware electronic system level design

Abstract

System-on-Chip (SoC) designers face many challenges to improve at the same time performance and energy efficiency, due to the continuous increase of the architecture complexity. Designers use Electronic System Level (ESL) tools and virtual prototyping to face this complexity in the early step of the system design. Power consumption includes dynamic power and static power. Power consumption and performance are adversely affected by supply voltage and frequency. This potential trade-off cannot be studied separately. Our work enhances an existing industrial performance model with the introduction of a new power-aware library, which allows a combined early power and performance analysis.