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16th IEEE International Workshop on Rapid System Prototyping (RSP'05)最新文献

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KoVer : a sophisticated residue arithmetic core generator KoVer:一个复杂的剩余算术核心发生器
16th IEEE International Workshop on Rapid System Prototyping (RSP'05) Pub Date : 2005-06-08 DOI: 10.1109/RSP.2005.27
Nikolaos Kostaras, H. T. Vergos
{"title":"KoVer : a sophisticated residue arithmetic core generator","authors":"Nikolaos Kostaras, H. T. Vergos","doi":"10.1109/RSP.2005.27","DOIUrl":"https://doi.org/10.1109/RSP.2005.27","url":null,"abstract":"Numerous architectures have been recently proposed for residue arithmetic components, each with its own speed, area and power consumption characteristics. In this paper, we present KoVer, a novel software tool that gives a designer the opportunity to explore several architectures for implementing his residue arithmetic blocks, select the one that best suits his goals and instantly get the HDL level description of the selected architecture.","PeriodicalId":262048,"journal":{"name":"16th IEEE International Workshop on Rapid System Prototyping (RSP'05)","volume":"24 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2005-06-08","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125536200","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 3
Modeling and prototyping of communication systems using Java: a case study 使用Java的通信系统建模和原型设计:一个案例研究
16th IEEE International Workshop on Rapid System Prototyping (RSP'05) Pub Date : 2005-06-08 DOI: 10.1109/RSP.2005.32
L. Indrusiak, Romualdo Begale Prudencio, M. Glesner
{"title":"Modeling and prototyping of communication systems using Java: a case study","authors":"L. Indrusiak, Romualdo Begale Prudencio, M. Glesner","doi":"10.1109/RSP.2005.32","DOIUrl":"https://doi.org/10.1109/RSP.2005.32","url":null,"abstract":"This paper presents a case study on the system level modeling of a WCDMA communication system using the Java object-oriented language. The modeling was done using Ptolemy II, a Java-based actor-oriented framework. The features of Ptolemy II and Java allowed us to implement a complete communication chain as a testbench, where the performance of the system could be evaluated under different channel models. Critical parts of the model were described in JHDL, a Java-based HDL, and a simulation ambassador was used to allow the co-simulation between Ptolemy II and JHDL modules. The final JHDL model was then prototyped in an FPGA.","PeriodicalId":262048,"journal":{"name":"16th IEEE International Workshop on Rapid System Prototyping (RSP'05)","volume":"6 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2005-06-08","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124438494","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 9
Test automation and safety assessment in rapid systems prototyping 快速系统原型中的测试自动化和安全评估
16th IEEE International Workshop on Rapid System Prototyping (RSP'05) Pub Date : 2005-06-08 DOI: 10.1109/RSP.2005.49
M. Auguston, J. Michael, M. Shing
{"title":"Test automation and safety assessment in rapid systems prototyping","authors":"M. Auguston, J. Michael, M. Shing","doi":"10.1109/RSP.2005.49","DOIUrl":"https://doi.org/10.1109/RSP.2005.49","url":null,"abstract":"This paper addresses the need for automatic generation of executable environment models to facilitate the testing of real-time reactive systems under development (SUD) in rapid system prototyping. We present an approach that allows users to model the environment in which the SUD will operate in the terms of attributed event grammar (AEG). The AEG provides a uniform approach for automatically generating, executing, and analyzing tests. The approach is supported by a generator that creates test cases from the AEG models. We demonstrate the effectiveness of the proposed approach with using as a case study a prototype of the safety-critical computer-assisted resuscitation algorithm (CARA) software for a casualty intravenous fluid infusion pump.","PeriodicalId":262048,"journal":{"name":"16th IEEE International Workshop on Rapid System Prototyping (RSP'05)","volume":"12 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2005-06-08","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128226604","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 7
An 8 GHz ultra wideband transceiver prototyping testbed 一个8ghz超宽带收发器原型测试平台
16th IEEE International Workshop on Rapid System Prototyping (RSP'05) Pub Date : 2005-06-08 DOI: 10.1109/RSP.2005.12
Deepak Argarwal, C. Anderson, P. Athanas
{"title":"An 8 GHz ultra wideband transceiver prototyping testbed","authors":"Deepak Argarwal, C. Anderson, P. Athanas","doi":"10.1109/RSP.2005.12","DOIUrl":"https://doi.org/10.1109/RSP.2005.12","url":null,"abstract":"Software defined radios have the potential of changing the fundamental usage model of wireless communications devices, but the capabilities of these transceivers are often limited by the speed of the underlying processors and FPGAs. This paper presents a testbed for the design of an impulse-based ultra wideband communication system. The transceiver is being developed using software/reconfigurable radio concepts and will be implemented using commercially available off-the-shelf components. The receiver uses eight 1 GHz ADCs to perform time interleaved sampling at an aggregate rate of 8 Gsamples/s. The high sampling rates present extraordinary demands on the down-conversion resources. The output of each ADC is in a different clock domain, with clocks offset in increments of 125 ps. Samples are captured by the high-speed ADC and processed using a Xilinx Virtex-II Pro (XC2VP70) FPGA. The testbed has two components: a non-real time part for data capture and signal acquisition, and a real-time part for data demodulation and signal processing. The non-real time component uses the internal block RAMs to store a set of samples and one of the PowerPC cores to process the data offline, to minimize logic resource usage. The real-time part uses distributed memory to store incoming data and processes it using hardwired multipliers and FPGA logic cells. The overall objective is to demonstrate a testbed that will allow researchers to evaluate different UWB modulation, multiple access, and coding schemes, and will support raw data rates of up to 100 MB/s.","PeriodicalId":262048,"journal":{"name":"16th IEEE International Workshop on Rapid System Prototyping (RSP'05)","volume":"4 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2005-06-08","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127801028","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 13
Accelerating a multiprocessor reconfigurable architecture with pipelined VLIW units 用流水线VLIW单元加速多处理器可重构体系结构
16th IEEE International Workshop on Rapid System Prototyping (RSP'05) Pub Date : 2005-06-08 DOI: 10.1109/RSP.2005.10
A. Azevedo, L. Agostini, F. Wagner, S. Bampi
{"title":"Accelerating a multiprocessor reconfigurable architecture with pipelined VLIW units","authors":"A. Azevedo, L. Agostini, F. Wagner, S. Bampi","doi":"10.1109/RSP.2005.10","DOIUrl":"https://doi.org/10.1109/RSP.2005.10","url":null,"abstract":"The X4CP32 is an architecture that combines the parallel and reconfigurable paradigms. It consists of a grid of reconfigurable and programming units (RPUs), each one containing 4 cells (including a microprocessor in each cell), responsible for all the processing and program flow. This paper presents architectural modifications in the X4CP32 in order to increase its performance. The RPU was implemented according to the VLIW (very long instruction word) methodology, and the cells were redesigned with a pipelined implementation. These improvements raised the maximum IPC of the RPU from 0.5 to 4 with an area overhead of 26%. To evaluate the new architecture, versions of the 2D discrete cosine transform, Montgomery modular multiplication and color space conversion were mapped, using the baseline architecture and the pipelined VLIW architecture.","PeriodicalId":262048,"journal":{"name":"16th IEEE International Workshop on Rapid System Prototyping (RSP'05)","volume":"41 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2005-06-08","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131091461","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 2
Custom instruction filter cache synthesis for low-power embedded systems 自定义指令滤波器缓存合成低功耗嵌入式系统
16th IEEE International Workshop on Rapid System Prototyping (RSP'05) Pub Date : 2005-06-08 DOI: 10.1109/RSP.2005.20
K. Vivekanandarajah, T. Srikanthan
{"title":"Custom instruction filter cache synthesis for low-power embedded systems","authors":"K. Vivekanandarajah, T. Srikanthan","doi":"10.1109/RSP.2005.20","DOIUrl":"https://doi.org/10.1109/RSP.2005.20","url":null,"abstract":"Filter cache has been shown to substantially reduce the power consumption in instruction memory hierarchy. Filter cache achieves energy savings due to the locality found in the frequent tiny loops, which are application dependent. In this paper we show that tuning filter cache to the needs of a particular application can save power and energy. Beside, a simple loop profiler directed methodology to deduce the optimal or near-optimal filter cache is proposed, without having to simulating all possible combinations of cache parameters from the specified space. Our experiments with MediaBench benchmark suite shows that the proposed methodology results in up to 49% energy reduction by tuning the filter cache. Moreover, the proposed filter cache tuning is done with the loop characteristics of the application, which in most cases are readily made available.","PeriodicalId":262048,"journal":{"name":"16th IEEE International Workshop on Rapid System Prototyping (RSP'05)","volume":"4 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2005-06-08","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133902264","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 14
Rapid prototyping of embedded software using selective formalism 使用选择性形式化的嵌入式软件快速原型
16th IEEE International Workshop on Rapid System Prototyping (RSP'05) Pub Date : 2005-06-08 DOI: 10.1109/RSP.2005.43
J. Carter, Ming Xu, W. B. Gardner
{"title":"Rapid prototyping of embedded software using selective formalism","authors":"J. Carter, Ming Xu, W. B. Gardner","doi":"10.1109/RSP.2005.43","DOIUrl":"https://doi.org/10.1109/RSP.2005.43","url":null,"abstract":"Our software synthesis tool, CSP++, generates C++ source code from verifiable CSPm specifications, and includes a framework for runtime execution. Our technique of selective formalism allows the synthesized formal control backbone code to be linked with non-formal user-coded C++ functions that carry out I/O and data processing. This tool already facilitates rapid prototyping of formally-specified software by bypassing the customary manual translation from a formal notation. In this work, we extend the rapid prototyping capability to SOPC (system on programmable chip) by targeting the CSP++ execution framework to an FPGA processor core. This is demonstrated with a new point-of-sale case study.","PeriodicalId":262048,"journal":{"name":"16th IEEE International Workshop on Rapid System Prototyping (RSP'05)","volume":"89 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2005-06-08","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133853716","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 7
A test selection language for CO-OPN specifications 用于CO-OPN规范的测试选择语言
16th IEEE International Workshop on Rapid System Prototyping (RSP'05) Pub Date : 2005-06-08 DOI: 10.1109/RSP.2005.9
L. Lucio, Luis Pedro, Didier Buchs
{"title":"A test selection language for CO-OPN specifications","authors":"L. Lucio, Luis Pedro, Didier Buchs","doi":"10.1109/RSP.2005.9","DOIUrl":"https://doi.org/10.1109/RSP.2005.9","url":null,"abstract":"In this paper we propose a test language that allows expressing test intentions for CO-OPN (concurrent object-oriented Petri nets) specifications - a formal specification language designed to handle large complex concurrent systems. Our test language is based on temporal logic formulas for expressing graphs of input/output pairs - the inputs correspond to operations performed on the system and the outputs to the observable results of those operations. We encapsulate the temporal logic using a language of constraints, which purpose is to shape the tests that are to be produced. In this paper we discuss the syntax and provide the semantics of this test language. One of our main worries while designing the test language were to keep it modular in order to promote reusability. Another worry was to be able to cope with non-determinism coming from the system under test. We illustrate managing non-determinism as well as other features of our language by showing how we can generate tests for the login part of an e-banking system. A framework for editing CO-OPN specifications exists and one of its features is the possibility of automatically generating high level Java prototypes that can be completed/extended by human developers. We discuss the applicability and the usefulness of our test language while verifying systems built using this methodology.","PeriodicalId":262048,"journal":{"name":"16th IEEE International Workshop on Rapid System Prototyping (RSP'05)","volume":"8 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2005-06-08","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133962625","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 4
A C/C++-based functional verification framework using the SystemC verification library 一个基于C/ c++的功能验证框架，使用了SystemC验证库
16th IEEE International Workshop on Rapid System Prototyping (RSP'05) Pub Date : 2005-06-08 DOI: 10.1109/RSP.2005.5
Sanggyu Park, S. Chae
{"title":"A C/C++-based functional verification framework using the SystemC verification library","authors":"Sanggyu Park, S. Chae","doi":"10.1109/RSP.2005.5","DOIUrl":"https://doi.org/10.1109/RSP.2005.5","url":null,"abstract":"This paper describes SoCBase-VL, which is a C/C++ based integrated framework for SoC functional verification. It has a layered architecture which provides easier test-bench description, automatic verification of bus interfaces and seamless testbench migration. This framework does not require verification engineers to learn other verification languages as long as they have sufficient knowledge on both C/C++ and SystemC. We have confirmed its usefulness by applying it to a TFT-LCD controller verification.","PeriodicalId":262048,"journal":{"name":"16th IEEE International Workshop on Rapid System Prototyping (RSP'05)","volume":"46 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2005-06-08","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124954350","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 10
A practical approach for circuit routing on dynamic reconfigurable devices 动态可重构器件电路布线的一种实用方法
16th IEEE International Workshop on Rapid System Prototyping (RSP'05) Pub Date : 2005-03-24 DOI: 10.1109/RSP.2005.7
A. Ahmadinia, C. Bobda, J. Ding, Mateusz Majer, J. Teich, S. Fekete, J. V. D. Veen
{"title":"A practical approach for circuit routing on dynamic reconfigurable devices","authors":"A. Ahmadinia, C. Bobda, J. Ding, Mateusz Majer, J. Teich, S. Fekete, J. V. D. Veen","doi":"10.1109/RSP.2005.7","DOIUrl":"https://doi.org/10.1109/RSP.2005.7","url":null,"abstract":"Management of communication by on-line routing in new FPGAs with a large amount of logic resources and partial re configurability is a new challenging problem. A network-on-chip (NoC) typically uses packet routing mechanism, which has often unsafe data transfers, and network interface overhead. In this paper, circuit routing for such dynamic NoCs is investigated, and a practical 1-dimensional network with an efficient routing algorithm is proposed and implemented. Also, this concept has been extended to the 2-dimensional case. The implementation results show the low area overhead and high performance of this network.","PeriodicalId":262048,"journal":{"name":"16th IEEE International Workshop on Rapid System Prototyping (RSP'05)","volume":"13 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2005-03-24","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123869575","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 62
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