16th IEEE International Workshop on Rapid System Prototyping (RSP'05)最新文献_第3页

Communication primitives driven hardware design and test methodology applied on complex video applications 应用于复杂视频应用的通信原语驱动的硬件设计和测试方法

16th IEEE International Workshop on Rapid System Prototyping (RSP'05) Pub Date : 2005-06-08 DOI: 10.1109/RSP.2005.17

A. Chirila-Rus, K. Denolf, B. Vanhoof, P. Schumacher, K. Vissers

引用次数: 7

On the use of rewriting logic for verification of distributed software architecture description based LfP 基于LfP的分布式软件体系结构描述验证中逻辑重写的应用

16th IEEE International Workshop on Rapid System Prototyping (RSP'05) Pub Date : 2005-06-08 DOI: 10.1109/RSP.2005.34

Chadlia Jerad, Kamel Barkaoui

引用次数: 11

Porting DSP applications across design tools using the dataflow interchange format 使用数据流交换格式跨设计工具移植DSP应用程序

16th IEEE International Workshop on Rapid System Prototyping (RSP'05) Pub Date : 2005-06-08 DOI: 10.1109/RSP.2005.39

Chia-Jui Hsu, S. Bhattacharyya

{"title":"Porting DSP applications across design tools using the dataflow interchange format","authors":"Chia-Jui Hsu, S. Bhattacharyya","doi":"10.1109/RSP.2005.39","DOIUrl":"https://doi.org/10.1109/RSP.2005.39","url":null,"abstract":"Modeling DSP applications through coarse-grain dataflow graphs is popular in the DSP design community, and a growing set of rapid prototyping tools support such dataflow semantics. Since different tools may be suitable for different phases or generations of a design, it is often desirable to migrate a dataflow-based application model from one prototyping tool to another. Two critical problems in transferring dataflow-based designs across different prototyping tools are the lack of a vendor-independent language for DSP-oriented dataflow graphs, and the lack of an efficient porting methodology. In our previous work, the dataflow interchange format (DIF) (C. Hsu et al., 2004) has been developed as a standard language to specify mixed-grain dataflow models for DSP systems. This paper presents the augmentation of the DIF infrastructure with a systematic porting approach that integrates DIF tightly with the specific exporting and importing mechanisms that interface DIF to specific DSP design tools. In conjunction with this porting mechanism, this paper also introduces a novel language, called the actor interchange format (AIF), for transferring relevant information pertaining to DSP library components across different tools. Through a case study of a synthetic aperture radar application, we demonstrate the high degree of automation offered by our DIF-based porting approach.","PeriodicalId":262048,"journal":{"name":"16th IEEE International Workshop on Rapid System Prototyping (RSP'05)","volume":"5 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2005-06-08","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125433419","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 11

Leveraging model representations for system level design tools 利用系统级设计工具的模型表示

16th IEEE International Workshop on Rapid System Prototyping (RSP'05) Pub Date : 2005-06-08 DOI: 10.1109/RSP.2005.28

J. Lapalme, E. Aboulhamid, G. Nicolescu

引用次数: 2

A rapid system prototyping platform for error control coding in optical CDMA networks 光学CDMA网络中差错控制编码的快速系统原型设计平台

16th IEEE International Workshop on Rapid System Prototyping (RSP'05) Pub Date : 2005-06-08 DOI: 10.1109/RSP.2005.8

M. Irman, J. Bajcsy

引用次数: 1

High level synthesis for data-driven applications 用于数据驱动应用程序的高级综合

16th IEEE International Workshop on Rapid System Prototyping (RSP'05) Pub Date : 2005-06-08 DOI: 10.1109/RSP.2005.26

E. Bergeron, Xavier Saint-Mleux, M. Feeley, J. David

{"title":"High level synthesis for data-driven applications","authors":"E. Bergeron, Xavier Saint-Mleux, M. Feeley, J. David","doi":"10.1109/RSP.2005.26","DOIUrl":"https://doi.org/10.1109/RSP.2005.26","url":null,"abstract":"John von Neumann proposed his famous architecture in a context where hardware was very expensive and bulky. His goal was to maximize functionality with minimal hardware. Presently, logical gates are nearly free and single chips contain billions of gates. However, most current designs are still based on Von Neumann's architecture because processors are built on this model. Nevertheless, the main current challenge is to be able to design, refine, synthesize and verify new architectures in a minimum time and with a maximum computational performance regardless of the gate count. Data driven architectures enable a high level of parallelism because instead of a single controller managing all the resources (and often a single ALU), tens or hundreds of small controllers can now operate in parallel on local processing units. This paper presents an environment for the high level description, refinement, synthesis and verification of such systems. Our own HDL is presented with its compiler and we show how it can be used as the intermediate language of a compiler for an even higher level functional programming language. Ongoing work enables the interfacing with other languages (from both hardware and software communities). We also intend to target asynchronous designs.","PeriodicalId":262048,"journal":{"name":"16th IEEE International Workshop on Rapid System Prototyping (RSP'05)","volume":"256 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2005-06-08","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121236548","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 7

Straight method for reallocation of complex cores by dynamic reconfiguration in Virtex II FPGAs Virtex II fpga中复杂核动态重构的直接重分配方法

16th IEEE International Workshop on Rapid System Prototyping (RSP'05) Pub Date : 2005-06-08 DOI: 10.1109/RSP.2005.45

Y. Krasteva, Ana B. Jimeno, E. D. L. Torre, T. Riesgo

引用次数: 38

Synthesis of communication structures and protocols in distributed embedded systems 分布式嵌入式系统中通信结构与协议的综合

16th IEEE International Workshop on Rapid System Prototyping (RSP'05) Pub Date : 2005-06-08 DOI: 10.1109/RSP.2005.47

Stefan Ihmor, Tobias Loke, W. Hardt

引用次数: 6

COMPASS - a novel concept of a reconfigurable platform for automotive system development and test COMPASS -一个用于汽车系统开发和测试的可重构平台的新概念

16th IEEE International Workshop on Rapid System Prototyping (RSP'05) Pub Date : 2005-06-08 DOI: 10.1109/RSP.2005.18

C. Bieser, K. Müller-Glaser

{"title":"COMPASS - a novel concept of a reconfigurable platform for automotive system development and test","authors":"C. Bieser, K. Müller-Glaser","doi":"10.1109/RSP.2005.18","DOIUrl":"https://doi.org/10.1109/RSP.2005.18","url":null,"abstract":"In this paper we present a new concept of a configurable modular rapid prototyping system called COMPASS (configurable modular platform for automotive systems). Our ambition is to support the design engineer in all phases of the rapid prototyping (RP) process, including the concept-oriented, the architecture-oriented and the realization-oriented RP. Therefore we provide one unique and flexible development platform that covers all phases. The overall performance and flexibility is reached by the special system structure and the intensive use of FPGAs in combination with a high performance processor. This offers the potential to implement automotive applications with highly specialized peripherals, fast interfaces and communication channels to cope with today's requirements. Moreover programmable logic devices allow hardware reuse to a very high degree in contrast to existing commercial products. The proposed platform saves costs since the versatile configurable interface cards can be used for different purposes and so feature benefits over function specific hardware modules. As a special bonus the flexible and adaptive structure of the platform associated with the reconfigurability of the modules is not only restricted to RP, but also permits the usage as a hardware-in-the-loop (HiL) test system.","PeriodicalId":262048,"journal":{"name":"16th IEEE International Workshop on Rapid System Prototyping (RSP'05)","volume":"33 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2005-06-08","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130652038","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 15

Dynamic reconfiguration of IP based systems 基于IP的系统的动态重构

16th IEEE International Workshop on Rapid System Prototyping (RSP'05) Pub Date : 2005-06-08 DOI: 10.1109/RSP.2005.23

M. Visarius, André Meisel, Markus Scheithauer, W. Hardt

引用次数: 6