Straight method for reallocation of complex cores by dynamic reconfiguration in Virtex II FPGAs

Abstract

Virtex II FPGAs are widely used in current designs because of their high density of logic cells and the availability of embedded DSP specific blocks (Multipliers) and Dual port RAMs along with the possibility of dynamic reconfiguration. Systems containing FPGAs could be updated once deployed by loading new configurations received, i.e., via a network connection. Unlike other approaches, which rely on more regular devices, i.e. the older Virtex FPGAs, this paper presents a solution for dynamic core insertion and reallocation that permits cores to make use of the embedded blocks available in Virtex II devices. An application called BITPOS is proposed. It extracts and reallocates Virtex II cores. It is compared with other similar solutions and a survey of existing core generation tools is presented. A feasible slot based architecture with a bus communication structure for reallocatable cores communication has been selected and applied in a prototype demonstrator.