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16th IEEE International Workshop on Rapid System Prototyping (RSP'05)最新文献

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Systematic design flow for fast hardware/software prototype generation from bus functional model for MPSoC 从总线功能模型快速生成MPSoC硬件/软件原型的系统设计流程
16th IEEE International Workshop on Rapid System Prototyping (RSP'05) Pub Date : 2005-06-08 DOI: 10.1109/RSP.2005.48
I. Petkov, P. Amblard, M. Hristov
{"title":"Systematic design flow for fast hardware/software prototype generation from bus functional model for MPSoC","authors":"I. Petkov, P. Amblard, M. Hristov","doi":"10.1109/RSP.2005.48","DOIUrl":"https://doi.org/10.1109/RSP.2005.48","url":null,"abstract":"System design at higher level of abstraction is a promising technique to deal with the increasing complexity of the modern embedded systems. Current MPSoC are designed at register transfer level. The bus functional model is a higher level of abstraction that allows the integration of heterogeneous hardware, software components and sophisticated communication interconnects to adapt different description models. This system abstraction model makes it possible to accelerate the simulation but ignores the accuracy of the developed circuit. This paper studies an example of system design transformation from a high level of abstraction to the physical prototype of a multiprocessor system on chip. With this work we propose a systematic and efficient design flow for system on chip integration from a bus functional level of abstraction towards physical prototyping of embedded systems. The flow is applied to accelerate an MPSoC example design.","PeriodicalId":262048,"journal":{"name":"16th IEEE International Workshop on Rapid System Prototyping (RSP'05)","volume":"9 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2005-06-08","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128326474","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 8
Rapid development methodology for customized middleware 用于定制中间件的快速开发方法
16th IEEE International Workshop on Rapid System Prototyping (RSP'05) Pub Date : 2005-06-08 DOI: 10.1109/RSP.2005.42
T. Vergnaud, J. Hugues, L. Pautet, F. Kordon
{"title":"Rapid development methodology for customized middleware","authors":"T. Vergnaud, J. Hugues, L. Pautet, F. Kordon","doi":"10.1109/RSP.2005.42","DOIUrl":"https://doi.org/10.1109/RSP.2005.42","url":null,"abstract":"Developing middleware for distributed application is a difficult challenge. Such software should be verifiable in order to help ensure its reliability; it also has to be configurable so that it can be tailored to the specific requirements of the target system. So there is a strong need for methodologies to manage numerous versions of such software. In this paper, we show the interest of architecture description languages (ADL) as a support for a development based on a prototyping process. We present our approach, which combines the Architecture Analysis & Design Language (AADL) and the schizophrenic middleware architecture, and show how those technologies can be used to design and configure verified middleware.","PeriodicalId":262048,"journal":{"name":"16th IEEE International Workshop on Rapid System Prototyping (RSP'05)","volume":"411 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2005-06-08","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124392541","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 7
Automated floating-point to fixed-point conversion with the fixify environment 使用fixify环境实现浮点到定点的自动转换
16th IEEE International Workshop on Rapid System Prototyping (RSP'05) Pub Date : 2005-06-08 DOI: 10.1109/RSP.2005.15
P. Belanovic, M. Rupp
{"title":"Automated floating-point to fixed-point conversion with the fixify environment","authors":"P. Belanovic, M. Rupp","doi":"10.1109/RSP.2005.15","DOIUrl":"https://doi.org/10.1109/RSP.2005.15","url":null,"abstract":"Conversion from floating-point to fixed-point formats is a necessary step in the design process of embedded systems and is traditionally performed manually. Automating this conversion process brings significant and much needed improvement in the efficiency of the design process. The fixify environment presented here fully automates the conversion process and comprises three optimization methods. The restricted-set full search algorithm is suited to designs that will be implemented on DSP cores and is, for such designs, guaranteed to find globally optimal solutions. On the other hand, the greedy search algorithm finds solution in the continuous search space and produces nearly optimal results, with the shortest required runtime. The branch-and-bound algorithm also works in the continuous search space and finds optimal solutions, but requires relatively long runtimes.","PeriodicalId":262048,"journal":{"name":"16th IEEE International Workshop on Rapid System Prototyping (RSP'05)","volume":"10 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2005-06-08","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124242141","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 61
Automatic generation of component wrappers by composition of hardware library elements starting from communication service specification 从通信服务规范开始，通过组合硬件库元素自动生成组件包装器
16th IEEE International Workshop on Rapid System Prototyping (RSP'05) Pub Date : 2005-06-08 DOI: 10.1109/RSP.2005.16
Arnaud Grasset, F. Rousseau, A. Jerraya
{"title":"Automatic generation of component wrappers by composition of hardware library elements starting from communication service specification","authors":"Arnaud Grasset, F. Rousseau, A. Jerraya","doi":"10.1109/RSP.2005.16","DOIUrl":"https://doi.org/10.1109/RSP.2005.16","url":null,"abstract":"A system-on-chip is composed of heterogeneous components interacting through a communication network. Wrappers are hardware components aimed to adapt these heterogeneous components to the network. Such an adaptation can be specified as a set of provided and required services, according to communication requirements and available resources. System-on-chip designers are required to quickly adapt to the fast changing system specifications, but the design of a wrapper can be time consuming. So this paper presents a new methodology for their automatic generation starting from a communication service specification. This specification, already used in the computer network community, is refined to an RTL model using a systematic library based approach. The effectiveness of the methodology is shown on an example.","PeriodicalId":262048,"journal":{"name":"16th IEEE International Workshop on Rapid System Prototyping (RSP'05)","volume":"27 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2005-06-08","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123623935","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 15
Heterogeneous modelling of an optical network-on-chip with SystemC 基于SystemC的片上光网络异构建模
16th IEEE International Workshop on Rapid System Prototyping (RSP'05) Pub Date : 2005-06-08 DOI: 10.1109/RSP.2005.25
M. Briere, E. Drouard, F. Mieyeville, D. Navarro, I. O’Connor, F. Gaffiot
{"title":"Heterogeneous modelling of an optical network-on-chip with SystemC","authors":"M. Briere, E. Drouard, F. Mieyeville, D. Navarro, I. O’Connor, F. Gaffiot","doi":"10.1109/RSP.2005.25","DOIUrl":"https://doi.org/10.1109/RSP.2005.25","url":null,"abstract":"This paper presents a heterogeneous model of an optical network-on chip (ONoC). An ONoC is an optical interconnect architecture integrated on a system-on-chip, and is intended to replace traditional electrical networks-on-chip (NoC) to overcome their future bandwidth limitations. To evaluate the advantages of a technological implementation of an ONoC, it is necessary to model its behavior and to realize a virtual prototype to estimate its power, latency, area, bandwidth, and subsequently to compare these parameters with the performance of a classical NoC. To model the ONoC at a high abstraction level, a rich system-level design language is used (SystemC). A bottom-up approach is used for the high level ONoC model description, and the performance values used at this level are extracted from the physical level with specific tools and models.","PeriodicalId":262048,"journal":{"name":"16th IEEE International Workshop on Rapid System Prototyping (RSP'05)","volume":"10 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2005-06-08","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127413540","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 47
Models for embedded application mapping onto NoCs: timing analysis 嵌入式应用映射到noc的模型:时序分析
16th IEEE International Workshop on Rapid System Prototyping (RSP'05) Pub Date : 2005-06-08 DOI: 10.1109/RSP.2005.33
C. Marcon, M. Kreutz, A. Susin, Ney Laert Vilar Calazans
{"title":"Models for embedded application mapping onto NoCs: timing analysis","authors":"C. Marcon, M. Kreutz, A. Susin, Ney Laert Vilar Calazans","doi":"10.1109/RSP.2005.33","DOIUrl":"https://doi.org/10.1109/RSP.2005.33","url":null,"abstract":"Networks-on-chip (NoCs) are an emergent communication infrastructure, which can be designed to deal with growing system complexity and technology evolution. The efficient use of NoCs needs techniques for application cores mapping, allowing reducing the message latency and consequently the overall execution time. To obtain mappings that fulfill the requirements during high-level design, appropriate models for NoCs and application cores become mandatory. High abstraction levels modeling may lead to unreliable estimates. On the other hand, detailed models may imply complex algorithms and high computational effort, with unacceptable computation time to get satisfactory results. NoC modeling for latency estimation requires capturing some infrastructure characteristics like topology and routing policies. Application cores models have to capture the application behavior, in terms of computation and/or communication. For instance, communication weighted models (CWM) and communication dependence model (CDM) consider only application communication aspects. However, the communication dependence and computation model (CDCM) consider both aspects of an application. This work compares these three models, according to their algorithm complexity and accuracy to model the application performance. We show that depending on the application characteristics, one of the models can be more suitable than the others.","PeriodicalId":262048,"journal":{"name":"16th IEEE International Workshop on Rapid System Prototyping (RSP'05)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2005-06-08","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130827565","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 13
Optimization techniques for ADL-driven RTL processor synthesis adl驱动RTL处理器合成的优化技术
16th IEEE International Workshop on Rapid System Prototyping (RSP'05) Pub Date : 2005-06-08 DOI: 10.1109/RSP.2005.36
O. Schliebusch, A. Chattopadhyay, E. M. Witte, D. Kammler, G. Ascheid, R. Leupers, H. Meyr
{"title":"Optimization techniques for ADL-driven RTL processor synthesis","authors":"O. Schliebusch, A. Chattopadhyay, E. M. Witte, D. Kammler, G. Ascheid, R. Leupers, H. Meyr","doi":"10.1109/RSP.2005.36","DOIUrl":"https://doi.org/10.1109/RSP.2005.36","url":null,"abstract":"Nowadays, architecture description languages (ADLs) are becoming popular for speeding up the development of complex SoC design, by performing design space exploration at a higher level of abstraction. This increase in the abstraction level traditionally comes at the cost of low performance of the final application specific instruction-set processor (ASIP) implementation, which is generated automatically from the ADL. There is a pressing need for novel optimization techniques for high level synthesis from ADLs, to compensate for this loss of performance. Two important aspects of these optimizations are the efficient usage of available structural information in the high level architecture descriptions and prudent pruning of overhead, introduced by mapping from ADL to register transfer level (RTL). In this paper, we present two high level optimization techniques, path sharing and decision minimization. These optimization techniques are shown to be of lower complexity, by at least two orders, compared to similar optimization during gate-level synthesis. The optimizations are tested for a RISC architecture, a VLIW architecture and two industrial embedded processors, Motorola M68HC11 and Infineon ICORE. The results indicate a significant improvement in overall performance.","PeriodicalId":262048,"journal":{"name":"16th IEEE International Workshop on Rapid System Prototyping (RSP'05)","volume":"35 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2005-06-08","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121763649","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 20
An approach for functional decomposition applied to state-based designs 一种应用于基于状态设计的功能分解方法
16th IEEE International Workshop on Rapid System Prototyping (RSP'05) Pub Date : 2005-06-08 DOI: 10.1109/RSP.2005.13
Luke Demoracski, D. Avresky
{"title":"An approach for functional decomposition applied to state-based designs","authors":"Luke Demoracski, D. Avresky","doi":"10.1109/RSP.2005.13","DOIUrl":"https://doi.org/10.1109/RSP.2005.13","url":null,"abstract":"This paper presents a new approach for functional decomposition of complex systems by applying and enhancing the concepts of clique-decomposition and superstate formation. This approach can be utilized by graphs and state-based software or hardware designs. This method extends the design flow process by automatically extracting states from an existing design and decomposing the states into submodules. The automatic state extraction can be performed either using an original tool or the existing Debussy nState tool. This method has been applied successfully to graphs and state-based Verilog programs, as illustrated by examples in this paper. Furthermore, the complexity analysis shows the underlying algorithm executes well.","PeriodicalId":262048,"journal":{"name":"16th IEEE International Workshop on Rapid System Prototyping (RSP'05)","volume":"25 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2005-06-08","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131508135","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Optimization of memory allocation for real-time video processing on FPGA 基于FPGA的实时视频处理内存分配优化
16th IEEE International Workshop on Rapid System Prototyping (RSP'05) Pub Date : 2005-06-08 DOI: 10.1109/RSP.2005.35
Benny Thörnberg, L. Olsson, M. O’nils
{"title":"Optimization of memory allocation for real-time video processing on FPGA","authors":"Benny Thörnberg, L. Olsson, M. O’nils","doi":"10.1109/RSP.2005.35","DOIUrl":"https://doi.org/10.1109/RSP.2005.35","url":null,"abstract":"We present an optimization model for the allocation of shift registers to dual ported FPGA memory blocks. Shift registers are used in real-time video processing for the storage of data flow dependencies. The model is formalized into a mixed integer linear program that can be executed using a general solver. Allocation results from realistic video systems verify the correctness of the model. This model serves as a formal specification and setup for the development of an efficient allocation heuristic.","PeriodicalId":262048,"journal":{"name":"16th IEEE International Workshop on Rapid System Prototyping (RSP'05)","volume":"26 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2005-06-08","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121796979","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 7
Performance evaluation of a NoC-based design for MC-CDMA telecommunications using NS-2 基于nos -2的MC-CDMA通信设计的性能评估
16th IEEE International Workshop on Rapid System Prototyping (RSP'05) Pub Date : 2005-06-08 DOI: 10.1109/RSP.2005.37
R. Lemaire, F. Clermidy, Y. Durand, D. Lattard, A. Jerraya
{"title":"Performance evaluation of a NoC-based design for MC-CDMA telecommunications using NS-2","authors":"R. Lemaire, F. Clermidy, Y. Durand, D. Lattard, A. Jerraya","doi":"10.1109/RSP.2005.37","DOIUrl":"https://doi.org/10.1109/RSP.2005.37","url":null,"abstract":"The trend nowadays is to integrate telecommunication system on complex SoC. But the requirements of such architecture in terms of interconnection and bandwidth constraints lead designers to propose innovative solutions such as networks-on-chip (NoC). In this paper we address a NoC-based implementation for a 4G modem. We propose a modelling environment based on a network simulation tool to evaluate its performance and set critical parameters. We present results validating our transceiver modem and showing the pertinence of the study for design exploration compared to other approaches.","PeriodicalId":262048,"journal":{"name":"16th IEEE International Workshop on Rapid System Prototyping (RSP'05)","volume":"10 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2005-06-08","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128155127","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 17
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