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16th IEEE International Workshop on Rapid System Prototyping (RSP'05)最新文献

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Discrete-continuous simulation model for accurate validation in component-based heterogeneous SoC design 基于组件的异构SoC设计中精确验证的离散-连续仿真模型
16th IEEE International Workshop on Rapid System Prototyping (RSP'05) Pub Date : 2005-06-08 DOI: 10.1109/RSP.2005.22
F. Bouchhima, G. Nicolescu, E. Aboulhamid, M. Abid
{"title":"Discrete-continuous simulation model for accurate validation in component-based heterogeneous SoC design","authors":"F. Bouchhima, G. Nicolescu, E. Aboulhamid, M. Abid","doi":"10.1109/RSP.2005.22","DOIUrl":"https://doi.org/10.1109/RSP.2005.22","url":null,"abstract":"Heterogeneous systems combining several technologies promise the overcoming of several limitations, cost constraints and provide new useful features. Currently their design is an important challenge, one of the key issues being the integration of the pre-built components specific to different application domains (ex. electrical, mechanical, optical, etc.). In this context, new CAD tools offering the global view of the systems to be designed and enabling their overall validation are mandatory. This paper presents a generic discrete-continuous simulation model for an accurate global validation in component-based heterogeneous systems design. This model allows using powerful tools for the two domains; it was applied for simulation of systems integrating discrete models in SystemC and continuous models in Simulink. Its evaluation was performed using an illustrative application.","PeriodicalId":262048,"journal":{"name":"16th IEEE International Workshop on Rapid System Prototyping (RSP'05)","volume":"4648 1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2005-06-08","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130351592","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 17
Design exploration and HW/SW rapid prototyping for real-time system design 实时系统设计的设计探索和硬件/软件快速原型设计
16th IEEE International Workshop on Rapid System Prototyping (RSP'05) Pub Date : 2005-06-08 DOI: 10.1109/RSP.2005.21
Sylvain Huet, E. Casseau, O. Pasquier
{"title":"Design exploration and HW/SW rapid prototyping for real-time system design","authors":"Sylvain Huet, E. Casseau, O. Pasquier","doi":"10.1109/RSP.2005.21","DOIUrl":"https://doi.org/10.1109/RSP.2005.21","url":null,"abstract":"Embedded signal processing systems are usually associated with real-time constraints and/or high data rates so that fully software implementation are often not satisfactory. In that case, mixed hardware/software implementations have to be investigated. However the increasing complexity of current applications makes classical design processes time consuming and consequently incompatible with an acceptable time to prototype. To address this problem, we propose a system-level design based methodology that aims at unifying the design flow from the functional description to the physical HW/SW implementation through functional and architectural flexibility. Our approach consists in automatically refining high abstraction level models through the use of an electronic system-level tool. We illustrate our methodology with the design of a wireless communication system.","PeriodicalId":262048,"journal":{"name":"16th IEEE International Workshop on Rapid System Prototyping (RSP'05)","volume":"13 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2005-06-08","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126867837","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 2
Test-time, run-time, and simulation-time temporal assertions in RSP RSP中的测试时、运行时和模拟时临时断言
16th IEEE International Workshop on Rapid System Prototyping (RSP'05) Pub Date : 2005-06-08 DOI: 10.1109/RSP.2005.50
D. Drusinsky, M. Shing, K. Demir
{"title":"Test-time, run-time, and simulation-time temporal assertions in RSP","authors":"D. Drusinsky, M. Shing, K. Demir","doi":"10.1109/RSP.2005.50","DOIUrl":"https://doi.org/10.1109/RSP.2005.50","url":null,"abstract":"For cost-effective prototyping, system designers should have a clear understanding of the intended use of the prototype under development. This paper describes a classification of formal specification (temporal) assertions used during system prototyping. The classification introduces two new classes of assertions in addition to the well-known class of test-time assertions: (i) assertions used only during simulation, and (ii) deployable assertions integrated with run-time control flow. Separating the formal specification into three distinct classes allows system designers to develop more effective prototypes to evaluate the different system behaviors and constraints. A prototype of a naval torpedo system is used to illustrate the concept.","PeriodicalId":262048,"journal":{"name":"16th IEEE International Workshop on Rapid System Prototyping (RSP'05)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2005-06-08","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129350545","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 13
Prototyping a residential gateway using Xilinx ISE 使用赛灵思ISE对住宅网关进行原型设计
16th IEEE International Workshop on Rapid System Prototyping (RSP'05) Pub Date : 2005-06-08 DOI: 10.1109/RSP.2005.40
S. W. Song, J. Zheng, W. B. Gardner
{"title":"Prototyping a residential gateway using Xilinx ISE","authors":"S. W. Song, J. Zheng, W. B. Gardner","doi":"10.1109/RSP.2005.40","DOIUrl":"https://doi.org/10.1109/RSP.2005.40","url":null,"abstract":"This paper presents a residential gateway (RG) prototyping process using Xilinx Integrated Software Environment (ISE) version 6.1i. The RG was designed for broadband residential multiservices based on a SONET over DWDM (dense wavelength division multiplexing) access network. The RG design was targeted for Xilinx Virtex II FPGA for prototyping purpose. The RG core design and the prototyping process using Xilinx ISE, including simulation and implementation, are discussed in this paper.","PeriodicalId":262048,"journal":{"name":"16th IEEE International Workshop on Rapid System Prototyping (RSP'05)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2005-06-08","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128704557","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
Performance improvement of multiprocessor simulation by optimizing synchronization and communication 通过优化同步和通信来提高多处理器仿真的性能
16th IEEE International Workshop on Rapid System Prototyping (RSP'05) Pub Date : 2005-06-08 DOI: 10.1109/RSP.2005.38
Moo-Kyoung Chung, H. Shim, C. Kyung
{"title":"Performance improvement of multiprocessor simulation by optimizing synchronization and communication","authors":"Moo-Kyoung Chung, H. Shim, C. Kyung","doi":"10.1109/RSP.2005.38","DOIUrl":"https://doi.org/10.1109/RSP.2005.38","url":null,"abstract":"This paper presents fast co-simulation techniques aimed at multiprocessor-based system-on-chip (SoC) design. Unlike existing co-simulation tools that use a centralized server, which manages clocks for all processor models and inter-processor communication, the proposed techniques separate the synchronization and communication and distribute the large portion of the tasks to each processor model. The amount of synchronization is reduced, and the message passing among the processor models through time-consuming inter-process communication (IPC) is removed. Fast processor model through automatically annotated native code execution is also introduced. We implemented these solutions in STIMUL, a co-simulation framework for multiprocessor system and achieved faster simulation speed by at least a factor of 10 over existing simulators.","PeriodicalId":262048,"journal":{"name":"16th IEEE International Workshop on Rapid System Prototyping (RSP'05)","volume":"10 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2005-06-08","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115771573","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
A HyperTransport chip-to-chip interconnect tunnel developed using SystemC 利用SystemC开发了一个HyperTransport片对片互连隧道
16th IEEE International Workshop on Rapid System Prototyping (RSP'05) Pub Date : 2005-06-08 DOI: 10.1109/RSP.2005.6
A. Castonguay, Y. Savaria
{"title":"A HyperTransport chip-to-chip interconnect tunnel developed using SystemC","authors":"A. Castonguay, Y. Savaria","doi":"10.1109/RSP.2005.6","DOIUrl":"https://doi.org/10.1109/RSP.2005.6","url":null,"abstract":"This paper presents a HyperTransport (HT) tunnel developed in hardware with SystemC. HT is an excellent technology for implementing flexible high performance system switch fabrics applicable to rapid system prototyping. An overview of the proposed architecture is presented, followed by synthesis results. Performance analysis shows that, when configured as an 8-bit link and implemented in a 0.18/spl mu/m CMOS standard cell technology, the design can operate at 400 mega transfers/s. This paper discusses the advantages and drawbacks of working with SystemC to perform large scale hardware implementations.","PeriodicalId":262048,"journal":{"name":"16th IEEE International Workshop on Rapid System Prototyping (RSP'05)","volume":"662 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2005-06-08","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116181778","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 5
Simulation of resolution of CS problem for multiple common variables in multiprocessor environment 多处理器环境下多公共变量的CS问题求解仿真
16th IEEE International Workshop on Rapid System Prototyping (RSP'05) Pub Date : 2005-06-08 DOI: 10.1109/RSP.2005.44
Ghulam Qader, M. Javed
{"title":"Simulation of resolution of CS problem for multiple common variables in multiprocessor environment","authors":"Ghulam Qader, M. Javed","doi":"10.1109/RSP.2005.44","DOIUrl":"https://doi.org/10.1109/RSP.2005.44","url":null,"abstract":"The high speed computing requires multitasking and parallel processing to increase the throughput of the system and optimizes use of system resources. In the multitasking environment, when a great number of processes execute in parallel, there may be some variables, which are common or shared between different numbers of processes. Due to this sharing, different critical sections are produced. The research work presented in this paper resolves the critical section (CS) problem of multiple common variables using multiprocessor environment. The development of a simulator for the resolution of CS problem has been presented. It is a comprehensive tool, which runs a simulation in real time and generates useful data for evaluation. A user-friendly and mouse-driven GUI has also been integrated. The developed system has been put through extensive experimentation. Results are taken using different sets of processes for different number of common variables on a number of processors. The evaluation results are very promising and could be used to further enhance performance of multi-user and multitasking operating systems running under different processors to deal with common variables.","PeriodicalId":262048,"journal":{"name":"16th IEEE International Workshop on Rapid System Prototyping (RSP'05)","volume":"144 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2005-06-08","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131589687","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Thread-level parallel execution in co-designed virtual machines 协同设计的虚拟机中的线程级并行执行
16th IEEE International Workshop on Rapid System Prototyping (RSP'05) Pub Date : 2005-06-08 DOI: 10.1109/RSP.2005.52
Thomas S. Hall, K. Kent
{"title":"Thread-level parallel execution in co-designed virtual machines","authors":"Thomas S. Hall, K. Kent","doi":"10.1109/RSP.2005.52","DOIUrl":"https://doi.org/10.1109/RSP.2005.52","url":null,"abstract":"Virtual machine technology is becoming more important as the use of non-heterogeneous computer networks have become more widespread. However, the runtime performance of an application running on a virtual machine is significantly below that of the same application running as a native executable on a given platform. Previous work shows that a hardware/software co-designed virtual machine can provide a performance improvement. This paper describes research work to further improve the performance of the co-designed virtual machine by adding thread-level parallel execution. The design put forward adds the functionality to support independent scheduling of threads in the hardware and software partitions of the co-designed virtual machine. A prototype of the design, based on the Java virtual machine, utilizing software simulation has been constructed and tested. The results of this testing show that the design is feasible when there is sufficient communication bandwidth available between the partitions.","PeriodicalId":262048,"journal":{"name":"16th IEEE International Workshop on Rapid System Prototyping (RSP'05)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2005-06-08","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130718037","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
The ordering of events in a prototyping platform 原型平台中事件的顺序
16th IEEE International Workshop on Rapid System Prototyping (RSP'05) Pub Date : 2005-06-08 DOI: 10.1109/RSP.2005.51
S. Dragone, Clemens Lombriser
{"title":"The ordering of events in a prototyping platform","authors":"S. Dragone, Clemens Lombriser","doi":"10.1109/RSP.2005.51","DOIUrl":"https://doi.org/10.1109/RSP.2005.51","url":null,"abstract":"The performance of software-based verification strategies is not keeping up with the increasing complexity of modern system-on-chip (SoC) designs. Therefore modular prototyping platforms are proposed to validate SoC designs. Most of these platforms consist of real processors combined with programmable logic, e.g. FPGA, that communicate through a board-level interconnect system. Usually, the programmable logic and the interconnect system do not run at the target clock speed of the future design. Hence, the emulated processes of the prototyping platform have to be synchronized to provide an accurate system validation. Most synchronization concepts are only able to synchronize the process data flows if data is time-independent. In this paper we present an event-based prototyping platform consisting of real processors combined with FPGAs. This platform emulates events with cycle accuracy, even though the processes operate in different scaled clock domains. Therefore we are able to validate time-dependent data flows.","PeriodicalId":262048,"journal":{"name":"16th IEEE International Workshop on Rapid System Prototyping (RSP'05)","volume":"62 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2005-06-08","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133257866","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
SyCE: an integrated environment for system design in SystemC SystemC中用于系统设计的集成环境
16th IEEE International Workshop on Rapid System Prototyping (RSP'05) Pub Date : 2005-06-08 DOI: 10.1109/RSP.2005.46
R. Drechsler, G. Fey, Christian Genz, Daniel Große
{"title":"SyCE: an integrated environment for system design in SystemC","authors":"R. Drechsler, G. Fey, Christian Genz, Daniel Große","doi":"10.1109/RSP.2005.46","DOIUrl":"https://doi.org/10.1109/RSP.2005.46","url":null,"abstract":"We present an integrated system design environment for SystemC, called SyCE. The system consists of several components for efficient analysis, verification and debugging of SystemC designs. The core tools are 1) ParSyC, a parser for SystemC designs that has also some synthesis options, 2) CheckSyC, a verification tool for formal equivalence checking, property checking and generating checkers for simulation or synthesis, 3) DeSyC, a tool for automatic debugging and error location in netlists, and 4) ViSyC, a visualization tool for schematic and source code view supporting cross-probing and annotation of simulation and debugging results. The tools fully support hierarchy and interact tightly. Designs can be described at different levels of abstraction.","PeriodicalId":262048,"journal":{"name":"16th IEEE International Workshop on Rapid System Prototyping (RSP'05)","volume":"16 6 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2005-06-08","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116750905","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 26
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