A HyperTransport chip-to-chip interconnect tunnel developed using SystemC

Abstract

This paper presents a HyperTransport (HT) tunnel developed in hardware with SystemC. HT is an excellent technology for implementing flexible high performance system switch fabrics applicable to rapid system prototyping. An overview of the proposed architecture is presented, followed by synthesis results. Performance analysis shows that, when configured as an 8-bit link and implemented in a 0.18/spl mu/m CMOS standard cell technology, the design can operate at 400 mega transfers/s. This paper discusses the advantages and drawbacks of working with SystemC to perform large scale hardware implementations.