M. Najibi, K. Saleh, M. Naderi, H. Pedram, M. Sedighi
{"title":"Prototyping globally asynchronous locally synchronous circuits on commercial synchronous FPGAs","authors":"M. Najibi, K. Saleh, M. Naderi, H. Pedram, M. Sedighi","doi":"10.1145/1046192.1046243","DOIUrl":"https://doi.org/10.1145/1046192.1046243","url":null,"abstract":"This paper introduces a methodology for prototyping globally asynchronous locally synchronous (GALS) circuits on synchronous commercial FPGAs. A library of required elements for implementing GALS circuits is proposed and general design considerations to successfully implement a GALS circuit on FPGA are discussed. The library includes clock generators and arbiters, and different port controllers. Different implementations of these circuits and their advantages and disadvantages are explored. At the end we present a GALS Reed-Solomon decoder as a practical example. The results show that the GALS approach improves the performance of the circuit by 11% and reduces the power consumption by 18.7% to 19,6% considering different error rates. On the other hand, the area of the circuit is increased by 51% which is acceptable considering that a pure synchronous circuit including a central controller is decomposed to generate GALS system and 29% of this overhead belongs to distributing controller in different modules. Deploying better decomposition methods can reduce this overhead substantially.","PeriodicalId":262048,"journal":{"name":"16th IEEE International Workshop on Rapid System Prototyping (RSP'05)","volume":"27 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2005-02-20","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133122151","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Ben Cordes, Jennifer G. Dy, M. Leeser, James Goebel
{"title":"Enabling a real-time solution for neuron detection with reconfigurable hardware","authors":"Ben Cordes, Jennifer G. Dy, M. Leeser, James Goebel","doi":"10.1145/1046192.1046232","DOIUrl":"https://doi.org/10.1145/1046192.1046232","url":null,"abstract":"FPGAs provide a speed advantage in processing for embedded systems, especially when processing is moved close to the sensors. Perhaps the ultimate embedded system is a neural prosthetic, where probes are inserted into the brain and recorded electrical activity is analyzed to determine which neurons have fired. In turn, this information can be used to manipulate an external device such as a robot arm or a computer mouse. To make the detection of these signals possible, some baseline data must be processed to correlate impulses to particular neurons. One method for processing this data uses a statistical clustering algorithm called expectation maximization, or EM. In this paper, we examine the EM clustering algorithm, determine the most computationally intensive portion, map it onto a reconfigurable device, and show several areas of performance gain.","PeriodicalId":262048,"journal":{"name":"16th IEEE International Workshop on Rapid System Prototyping (RSP'05)","volume":"14 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2005-02-20","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129991228","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}