{"title":"基于FPGA的实时视频处理内存分配优化","authors":"Benny Thörnberg, L. Olsson, M. O’nils","doi":"10.1109/RSP.2005.35","DOIUrl":null,"url":null,"abstract":"We present an optimization model for the allocation of shift registers to dual ported FPGA memory blocks. Shift registers are used in real-time video processing for the storage of data flow dependencies. The model is formalized into a mixed integer linear program that can be executed using a general solver. Allocation results from realistic video systems verify the correctness of the model. This model serves as a formal specification and setup for the development of an efficient allocation heuristic.","PeriodicalId":262048,"journal":{"name":"16th IEEE International Workshop on Rapid System Prototyping (RSP'05)","volume":"26 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2005-06-08","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"7","resultStr":"{\"title\":\"Optimization of memory allocation for real-time video processing on FPGA\",\"authors\":\"Benny Thörnberg, L. Olsson, M. O’nils\",\"doi\":\"10.1109/RSP.2005.35\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"We present an optimization model for the allocation of shift registers to dual ported FPGA memory blocks. Shift registers are used in real-time video processing for the storage of data flow dependencies. The model is formalized into a mixed integer linear program that can be executed using a general solver. Allocation results from realistic video systems verify the correctness of the model. This model serves as a formal specification and setup for the development of an efficient allocation heuristic.\",\"PeriodicalId\":262048,\"journal\":{\"name\":\"16th IEEE International Workshop on Rapid System Prototyping (RSP'05)\",\"volume\":\"26 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"2005-06-08\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"7\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"16th IEEE International Workshop on Rapid System Prototyping (RSP'05)\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/RSP.2005.35\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"16th IEEE International Workshop on Rapid System Prototyping (RSP'05)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/RSP.2005.35","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
Optimization of memory allocation for real-time video processing on FPGA
We present an optimization model for the allocation of shift registers to dual ported FPGA memory blocks. Shift registers are used in real-time video processing for the storage of data flow dependencies. The model is formalized into a mixed integer linear program that can be executed using a general solver. Allocation results from realistic video systems verify the correctness of the model. This model serves as a formal specification and setup for the development of an efficient allocation heuristic.
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