An 8 GHz ultra wideband transceiver prototyping testbed

Abstract

Software defined radios have the potential of changing the fundamental usage model of wireless communications devices, but the capabilities of these transceivers are often limited by the speed of the underlying processors and FPGAs. This paper presents a testbed for the design of an impulse-based ultra wideband communication system. The transceiver is being developed using software/reconfigurable radio concepts and will be implemented using commercially available off-the-shelf components. The receiver uses eight 1 GHz ADCs to perform time interleaved sampling at an aggregate rate of 8 Gsamples/s. The high sampling rates present extraordinary demands on the down-conversion resources. The output of each ADC is in a different clock domain, with clocks offset in increments of 125 ps. Samples are captured by the high-speed ADC and processed using a Xilinx Virtex-II Pro (XC2VP70) FPGA. The testbed has two components: a non-real time part for data capture and signal acquisition, and a real-time part for data demodulation and signal processing. The non-real time component uses the internal block RAMs to store a set of samples and one of the PowerPC cores to process the data offline, to minimize logic resource usage. The real-time part uses distributed memory to store incoming data and processes it using hardwired multipliers and FPGA logic cells. The overall objective is to demonstrate a testbed that will allow researchers to evaluate different UWB modulation, multiple access, and coding schemes, and will support raw data rates of up to 100 MB/s.