{"title":"KoVer:一个复杂的剩余算术核心发生器","authors":"Nikolaos Kostaras, H. T. Vergos","doi":"10.1109/RSP.2005.27","DOIUrl":null,"url":null,"abstract":"Numerous architectures have been recently proposed for residue arithmetic components, each with its own speed, area and power consumption characteristics. In this paper, we present KoVer, a novel software tool that gives a designer the opportunity to explore several architectures for implementing his residue arithmetic blocks, select the one that best suits his goals and instantly get the HDL level description of the selected architecture.","PeriodicalId":262048,"journal":{"name":"16th IEEE International Workshop on Rapid System Prototyping (RSP'05)","volume":"24 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2005-06-08","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"3","resultStr":"{\"title\":\"KoVer : a sophisticated residue arithmetic core generator\",\"authors\":\"Nikolaos Kostaras, H. T. Vergos\",\"doi\":\"10.1109/RSP.2005.27\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"Numerous architectures have been recently proposed for residue arithmetic components, each with its own speed, area and power consumption characteristics. In this paper, we present KoVer, a novel software tool that gives a designer the opportunity to explore several architectures for implementing his residue arithmetic blocks, select the one that best suits his goals and instantly get the HDL level description of the selected architecture.\",\"PeriodicalId\":262048,\"journal\":{\"name\":\"16th IEEE International Workshop on Rapid System Prototyping (RSP'05)\",\"volume\":\"24 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"2005-06-08\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"3\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"16th IEEE International Workshop on Rapid System Prototyping (RSP'05)\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/RSP.2005.27\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"16th IEEE International Workshop on Rapid System Prototyping (RSP'05)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/RSP.2005.27","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
KoVer : a sophisticated residue arithmetic core generator
Numerous architectures have been recently proposed for residue arithmetic components, each with its own speed, area and power consumption characteristics. In this paper, we present KoVer, a novel software tool that gives a designer the opportunity to explore several architectures for implementing his residue arithmetic blocks, select the one that best suits his goals and instantly get the HDL level description of the selected architecture.