2015 IEEE 24th Asian Test Symposium (ATS)最新文献

An Integrated Approach for Improving Compression and Diagnostic Properties of Test Sets 一种提高测试集压缩和诊断性能的综合方法

2015 IEEE 24th Asian Test Symposium (ATS) Pub Date : 2015-11-22 DOI: 10.1109/ATS.2015.33

Srinivasa Shashank Nuthakki, S. Chattopadhyay

引用次数: 1

On Improving Transition Test Set Quality to Detect CMOS Transistor Stuck-Open Faults 提高过渡测试集质量检测CMOS晶体管卡断故障

2015 IEEE 24th Asian Test Symposium (ATS) Pub Date : 2015-11-22 DOI: 10.1109/ATS.2015.24

X. Lin, Wu-Tung Cheng, J. Rajski

引用次数: 10

A Lightweight Timing Channel Protection for Shared Memory Controllers 一种用于共享内存控制器的轻量级定时通道保护

2015 IEEE 24th Asian Test Symposium (ATS) Pub Date : 2015-11-22 DOI: 10.1109/ATS.2015.17

Guopei Liu, Ying Wang, Sen Li, Huawei Li, Xiaowei Li

引用次数: 0

SDC-TPG: A Deterministic Zero-Inflation Parallel Test Pattern Generator 一个确定的零膨胀并行测试模式生成器

2015 IEEE 24th Asian Test Symposium (ATS) Pub Date : 2015-11-22 DOI: 10.1109/ATS.2015.15

Chun-Hao Chang, Kuen-Wei Yeh, Jiun-Lang Huang, Laung-Terng Wang

引用次数: 4

A Test Generation Method for Data Paths Using Easily Testable Functional Time Expansion Models and Controller Augmentation 一种使用易于测试的功能时间展开模型和控制器扩展的数据路径测试生成方法

2015 IEEE 24th Asian Test Symposium (ATS) Pub Date : 2015-11-22 DOI: 10.1109/ATS.2015.14

Tetsuya Masuda, Jun Nishimaki, Toshinori Hosokawa, H. Fujiwara

{"title":"A Test Generation Method for Data Paths Using Easily Testable Functional Time Expansion Models and Controller Augmentation","authors":"Tetsuya Masuda, Jun Nishimaki, Toshinori Hosokawa, H. Fujiwara","doi":"10.1109/ATS.2015.14","DOIUrl":"https://doi.org/10.1109/ATS.2015.14","url":null,"abstract":"In recent years, various high-level test synthesis methods for data paths have been proposed for the improvement in design productivity and test cost reduction. Most of the approaches assume that controllers and data paths are isolated from each other, and hence the hardware overhead becomes large. On the other hand, the approach without separation of a controller and a data path usually decreases the testability. To resolve this problem, an approach that augments a controller by adding extra control functions to make a data path easily testable was proposed. However, the approach cannot always succeed in generating test sequences with high fault coverage if a general ATPG tool is used without knowing any information of augmented control functions. In this paper, we introduce \"easily testable functional time expansion models for data paths\", and propose a test generation method for data paths using easily testable functional time expansion models and controller augmentation such that easily testable functional time expansion models are controllable. Experimental results show the effectiveness of the proposed method for high level synthesis benchmark circuits.","PeriodicalId":256879,"journal":{"name":"2015 IEEE 24th Asian Test Symposium (ATS)","volume":"201 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2015-11-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123030879","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 8

SHAKTI-F: A Fault Tolerant Microprocessor Architecture 一种容错微处理器体系结构

2015 IEEE 24th Asian Test Symposium (ATS) Pub Date : 2015-11-22 DOI: 10.1109/ATS.2015.35

Sukrat Gupta, Neel Gala, G. Madhusudan, V. Kamakoti

{"title":"SHAKTI-F: A Fault Tolerant Microprocessor Architecture","authors":"Sukrat Gupta, Neel Gala, G. Madhusudan, V. Kamakoti","doi":"10.1109/ATS.2015.35","DOIUrl":"https://doi.org/10.1109/ATS.2015.35","url":null,"abstract":"Deeply scaled CMOS circuits are vulnerable to soft and hard errors. These errors pose reliability concerns, especially for systems used in radiation-prone environments like space and nuclear applications. This paper presents SHAKTI-F, a RISC-V based SEE-tolerant micro-processor architecture that provides a solution to the reliability issues mentioned above. The proposed architecture uses error correcting codes (ECC) to tolerate errors in registers and memories, while it employs a combination of space and time redundancy based techniques to tolerate errors in the ALU. Two novel re-computation techniques for detecting errors for the addition/subtraction and multiplication modules are proposed. The scheme also identifies parts of the circuitry that need to be radiation hardened thus providing a total protection to SEEs. The proposed scheme provides fine-grain error detection capability that help in localization of the error to a specific functional unit and isolating the same, rather than the entire processor or a large module within a processor. This provides a graceful degradation and/or fail-safe shutdown capability to the processor. The HDL model of the processor was validated by simulating it with randomly induced SEEs. The proposed scheme adds an extra penalty of only 20% on the core area and 25% penalty on the performance when compared with conventional systems. This is very less when compared to the penalty incurred by employing schemes including double modular and triple modular redundancy. Interestingly, there is a 45% reduction in power consumption due to introduction of fault tolerance. The resulting system runs at 330 MHz on a 55nm technology node, which is sufficient for the class of applications these cores are utilized for.","PeriodicalId":256879,"journal":{"name":"2015 IEEE 24th Asian Test Symposium (ATS)","volume":"308 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2015-11-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133088083","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 26

In-Circuit Mutation-Based Automatic Correction of Certain Design Errors Using SAT Mechanisms 基于SAT机制的基于电路突变的某些设计错误自动校正

2015 IEEE 24th Asian Test Symposium (ATS) Pub Date : 2015-11-22 DOI: 10.1109/ATS.2015.41

Payman Behnam, B. Alizadeh

引用次数: 14

A Technique for Analyzing On-Chip Power Supply Impedance 片上电源阻抗分析技术

2015 IEEE 24th Asian Test Symposium (ATS) Pub Date : 2015-11-22 DOI: 10.1109/ATS.2015.40

M. Ishida, T. Nakura, Akira Matsukawa, R. Ikeno, K. Asada

引用次数: 0

Diagnostic Tests and Diagnosis for Delay Faults Using Path Segmentation 使用路径分割的延迟故障诊断测试和诊断

2015 IEEE 24th Asian Test Symposium (ATS) Pub Date : 2015-11-22 DOI: 10.1109/ATS.2015.32

Tino Flenker, André Sülflow, G. Fey

引用次数: 2

A Novel Scan Segmentation Design for Power Controllability and Reduction in At-Speed Test 一种用于高速测试中功率可控性和降低的新型扫描分割设计

2015 IEEE 24th Asian Test Symposium (ATS) Pub Date : 2015-11-22 DOI: 10.1109/ATS.2015.9

Z. Jiang, D. Xiang, Kele Shen

{"title":"A Novel Scan Segmentation Design for Power Controllability and Reduction in At-Speed Test","authors":"Z. Jiang, D. Xiang, Kele Shen","doi":"10.1109/ATS.2015.9","DOIUrl":"https://doi.org/10.1109/ATS.2015.9","url":null,"abstract":"The increasing power consumption during the chip testing process has become the bottleneck of chip production and testing for micro-nano VLSI circuits. Numerous low power design-for-testability (DfT) techniques have been proposed to deal with the test power problem, and segmented scan method was shown to be an efficient solution. We propose a new power-aware scan segment architecture, which can accurately control the power of shift and capture cycles at the same time. Since enabling only a subset of scan flip-flops to capture test responses in one cycle compromises the fault coverage, we propose a new method to reduce the fault coverage loss. First, we use a more accurate notion, spoiled nodes, instead of violation edges used in previous works to analyse the ependency of flip-flops, then we use simulated annealing(SA) mechanism to find the best combination of these flip-flops while considering the clock trees' impact. To the best of our knowledge, this is the first work to make shift and capture power in a controllable way with minimum fault coverage loss, small test-data volume and no extra hardware overhead for at-speed transition fault test. Extensive experiments have been performed on reference circuit ISCAS89 and IWLS2005 to verify the effectiveness of the proposed method.","PeriodicalId":256879,"journal":{"name":"2015 IEEE 24th Asian Test Symposium (ATS)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2015-11-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129682608","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 8