Guopei Liu, Ying Wang, Sen Li, Huawei Li, Xiaowei Li
{"title":"一种用于共享内存控制器的轻量级定时通道保护","authors":"Guopei Liu, Ying Wang, Sen Li, Huawei Li, Xiaowei Li","doi":"10.1109/ATS.2015.17","DOIUrl":null,"url":null,"abstract":"With the growth of cloud computing, security and privacy is becoming more and more important. Timing channel attack is one of the most remarkable security threads for memory controllers due to competition for shared resources. However, the existing protection strategies that ensure the deterministic of memory accesses by dividing bandwidth introduce great latency and performance degradation. This paper proposes a refresh hiding approach that adjusts the refresh operations to multiplex refresh time with additional latency introduced by those bandwidth division strategies. The experiment results show refresh hiding can reduce more than 20% of program runtime, and it will be more efficient as DRAM density increases.","PeriodicalId":256879,"journal":{"name":"2015 IEEE 24th Asian Test Symposium (ATS)","volume":"94 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2015-11-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"0","resultStr":"{\"title\":\"A Lightweight Timing Channel Protection for Shared Memory Controllers\",\"authors\":\"Guopei Liu, Ying Wang, Sen Li, Huawei Li, Xiaowei Li\",\"doi\":\"10.1109/ATS.2015.17\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"With the growth of cloud computing, security and privacy is becoming more and more important. Timing channel attack is one of the most remarkable security threads for memory controllers due to competition for shared resources. However, the existing protection strategies that ensure the deterministic of memory accesses by dividing bandwidth introduce great latency and performance degradation. This paper proposes a refresh hiding approach that adjusts the refresh operations to multiplex refresh time with additional latency introduced by those bandwidth division strategies. The experiment results show refresh hiding can reduce more than 20% of program runtime, and it will be more efficient as DRAM density increases.\",\"PeriodicalId\":256879,\"journal\":{\"name\":\"2015 IEEE 24th Asian Test Symposium (ATS)\",\"volume\":\"94 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"2015-11-22\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"0\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"2015 IEEE 24th Asian Test Symposium (ATS)\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/ATS.2015.17\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"2015 IEEE 24th Asian Test Symposium (ATS)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/ATS.2015.17","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
A Lightweight Timing Channel Protection for Shared Memory Controllers
With the growth of cloud computing, security and privacy is becoming more and more important. Timing channel attack is one of the most remarkable security threads for memory controllers due to competition for shared resources. However, the existing protection strategies that ensure the deterministic of memory accesses by dividing bandwidth introduce great latency and performance degradation. This paper proposes a refresh hiding approach that adjusts the refresh operations to multiplex refresh time with additional latency introduced by those bandwidth division strategies. The experiment results show refresh hiding can reduce more than 20% of program runtime, and it will be more efficient as DRAM density increases.