In-Circuit Mutation-Based Automatic Correction of Certain Design Errors Using SAT Mechanisms

Abstract

A large amount of time and effort must be spent to ensure the correctness of a digital design. Although many Computer Aided Design (CAD) solutions have been provided to enhance efficiency of existing debugging approaches, they are suffering from shortage of efficient automatic correction mechanisms. In this paper, we introduce an in-circuit mutation technique for correcting design bugs in digital designs. The aim of this work is reducing correction time by connecting primitive gates into inputs of 6-to-1 multiplexers in the place of potential bugs and utilizing satisfiability (SAT) engine for choosing the correct gates. The empirical results demonstrate that our proposed method can correct multiple bugs in a design by targeting gate replacements and wires exchanges efficiently. Average improvements in terms of the runtime and success rate in correction for combinational circuits in comparison with the latest the existing method are 3.4× and 11.5%, respectively. These results for sequential circuits are 3.8× and 17% respectively.