2015 IEEE 24th Asian Test Symposium (ATS)最新文献_第2页

At-Speed Testing of Inter-Die Connections of 3D-SICs in the Presence of Shore Logic Shore逻辑存在下3d - sic模间连接的高速测试

2015 IEEE 24th Asian Test Symposium (ATS) Pub Date : 2015-11-22 DOI: 10.1109/ATS.2015.21

K. Shibin, V. Chickermane, B. Keller, C. Papameletis, E. Marinissen

引用次数: 18

Intermittent and Transient Fault Diagnosis on Sparse Code Signatures 稀疏码签名的间歇和瞬态故障诊断

2015 IEEE 24th Asian Test Symposium (ATS) Pub Date : 2015-11-22 DOI: 10.1109/ATS.2015.34

M. Kochte, Atefe Dalirsani, Andrea Bernabei, M. Omaña, C. Metra, H. Wunderlich

{"title":"Intermittent and Transient Fault Diagnosis on Sparse Code Signatures","authors":"M. Kochte, Atefe Dalirsani, Andrea Bernabei, M. Omaña, C. Metra, H. Wunderlich","doi":"10.1109/ATS.2015.34","DOIUrl":"https://doi.org/10.1109/ATS.2015.34","url":null,"abstract":"Failure diagnosis of field returns typically requires high quality test stimuli and assumes that tests can be repeated. For intermittent faults with fault activation conditions depending on the physical environment, the repetition of tests cannot ensure that the behavior in the field is also observed during diagnosis, causing field returns diagnosed as no-trouble-found. In safety critical applications, self-checking circuits, which provide concurrent error detection, are frequently used. To diagnose intermittent and transient faulty behavior in such circuits, we use the stored encoded circuit outputs in case of a failure (called signatures) for later analysis in diagnosis. For the first time, a diagnosis algorithm is presented that is capable of performing the classification of intermittent or transient faults using only the very limited amount of functional stimuli and signatures observed during operation and stored on chip. The experimental results demonstrate that even with these harsh limitations it is possible to distinguish intermittent from transient faulty behavior. This is essential to determine whether a circuit in which failures have been observed should be subject to later physical failure analysis, since intermittent faulty behavior has been diagnosed. In case of transient faulty behavior, it may still be operated reliably.","PeriodicalId":256879,"journal":{"name":"2015 IEEE 24th Asian Test Symposium (ATS)","volume":"51 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2015-11-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127888274","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 2

A Soft Error Resilient Low Leakage SRAM Cell Design 一种软错误弹性低漏SRAM单元设计

2015 IEEE 24th Asian Test Symposium (ATS) Pub Date : 2015-11-22 DOI: 10.1109/ATS.2015.30

M. AdithyalalP., S. Balachandran, Virendra Singh

引用次数: 0

Challenge Engineering and Design of Analog Push Pull Amplifier Based Physically Unclonable Function for Hardware Security 基于物理不可克隆功能的模拟推拉放大器硬件安全挑战工程与设计

2015 IEEE 24th Asian Test Symposium (ATS) Pub Date : 2015-11-22 DOI: 10.1109/ATS.2015.29

Sabyasachi Deyati, B. Muldrey, A. Singh, A. Chatterjee

{"title":"Challenge Engineering and Design of Analog Push Pull Amplifier Based Physically Unclonable Function for Hardware Security","authors":"Sabyasachi Deyati, B. Muldrey, A. Singh, A. Chatterjee","doi":"10.1109/ATS.2015.29","DOIUrl":"https://doi.org/10.1109/ATS.2015.29","url":null,"abstract":"In the recent past, Physically Unclonable Functions (PUFs) have been proposed as a way of implementing security in modern ICs. PUFs are hardware designs that exploit the randomness in silicon manufacturing processes to create IC-specific signatures for silicon authentication. While prior PUF designs have been largely digital, in this work we propose a novel PUF design based on transfer function variability of an analog push-pull amplifier under process variations. A differential amplifier architecture is proposed with digital interfaces to allow the PUF to be used in digital as well as mixed-signal SoCs. A key innovation is digital stimulus engineering for the analog amplifier that allows 2X improvements in the uniqueness of IC signatures generated over arbiter-based digital PUF architectures, while maintaining high signature reliability over +/- 10 % voltage and -20 to 120 degree Celsius temperature variation. The proposed PUF is also resistive to model building attacks as the internal analog operation of the PUF is difficult to reverse-engineer due to the continuum of internal states involved. We show the benefits of the proposed PUF through comparison with a traditional arbiter-based digital PUF using simulation experiments.","PeriodicalId":256879,"journal":{"name":"2015 IEEE 24th Asian Test Symposium (ATS)","volume":"176 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2015-11-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116328420","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 8

A New Approach for Minimal Environment Construction for Modular Property Verification 模块化特性验证的最小环境构造新方法

2015 IEEE 24th Asian Test Symposium (ATS) Pub Date : 2015-11-22 DOI: 10.1109/ATS.2015.42

Saikat Dutta, S. Chattopadhyay, A. Banerjee, P. Dasgupta

引用次数: 0

FPGA Implementation of High Speed Latency Optimized Optical Communication System Based on Orthogonal Concatenated Code 基于正交级联码的高速时延优化光通信系统的FPGA实现

2015 IEEE 24th Asian Test Symposium (ATS) Pub Date : 2015-11-22 DOI: 10.1109/ATS.2015.36

S. Mandal, S. Sau, A. Chakrabarti, S. Pal, S. Chattopadhyay

{"title":"FPGA Implementation of High Speed Latency Optimized Optical Communication System Based on Orthogonal Concatenated Code","authors":"S. Mandal, S. Sau, A. Chakrabarti, S. Pal, S. Chattopadhyay","doi":"10.1109/ATS.2015.36","DOIUrl":"https://doi.org/10.1109/ATS.2015.36","url":null,"abstract":"There is an immense need of very high speed robust data communication in many critical applications like radar communication, satellite communication, high energy physics experiment (HEP) and biomedical instrumentation etc. Transient errors due to radiation and other environmental hazards are responsible to create some temporary malfunctions in such high speed communication system. Concatenated code can make the high speed communication more robust against transient errors. This paper presents a novel design of latency optimized optical communication system involving orthogonal concatenated code generated through BCH code (named after Raj Bose and D. K. Ray-Chaudhuri) and Hamming code as component code and its efficient implementation on hardware using Kintex-7 FPGA board. Our design optimizes the transmission latency of the system to a great extent and makes it extremely efficient for real time high data rate applications. We have successfully tested our design for board to board communication over latency optimized optical link at ~5 Gbps data rate. Resource utilization, power estimation and bit error rate (BER) of our implemented system are also reported.","PeriodicalId":256879,"journal":{"name":"2015 IEEE 24th Asian Test Symposium (ATS)","volume":"37 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2015-11-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125010801","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 1

Logic/Clock-Path-Aware At-Speed Scan Test Generation for Avoiding False Capture Failures and Reducing Clock Stretch 逻辑/时钟路径感知的快速扫描测试生成，以避免错误捕获失败和减少时钟拉伸

2015 IEEE 24th Asian Test Symposium (ATS) Pub Date : 2015-11-22 DOI: 10.1109/ATS.2015.25

K. Asada, X. Wen, S. Holst, K. Miyase, S. Kajihara, M. Kochte, E. Schneider, H. Wunderlich, J. Qian

引用次数: 7

Testing Inter-Word Coupling Faults of Wide I/O DRAMs 宽I/O dram的字间耦合故障测试

2015 IEEE 24th Asian Test Symposium (ATS) Pub Date : 2015-11-22 DOI: 10.1109/ATS.2015.19

Che-Wei Chou, Yong-Xiao Chen, Jin-Fu Li

引用次数: 0

Analysis of Soft Error Propagation Considering Masking Effects on Re-Convergent Path 考虑再收敛路径掩蔽效应的软误差传播分析

2015 IEEE 24th Asian Test Symposium (ATS) Pub Date : 2015-11-22 DOI: 10.1109/ATS.2015.31

Y. Kimi, Go Matsukawa, Shuhei Yoshida, S. Izumi, H. Kawaguchi, M. Yoshimoto

{"title":"Analysis of Soft Error Propagation Considering Masking Effects on Re-Convergent Path","authors":"Y. Kimi, Go Matsukawa, Shuhei Yoshida, S. Izumi, H. Kawaguchi, M. Yoshimoto","doi":"10.1109/ATS.2015.31","DOIUrl":"https://doi.org/10.1109/ATS.2015.31","url":null,"abstract":"As technology nodes continue to shrink, the impact of radiation-induced soft error on processor reliability increases. Estimation of processor reliability and identification of vulnerable flip-flops requires accurate soft error rate (SER) analysis techniques. This paper presents a proposal for a soft error propagation analysis technique. We specifically examine single event upset (SEU) occurring at a flip-flop in sequential circuits. When SEUs propagate in sequential circuits, the faults can be masked temporally and logically. Conventional soft error propagation analysis techniques do not consider error convergent timing on re-convergent paths. The proposed technique can analyze soft error propagation while considering error-convergent timing on a re-convergent path by combinational analysis of temporal and logical effects. The proposed technique also considers the case in which the temporal masking is disabled with an enable signal of the erroneous flip-flop negated. Experimental results show that the proposed technique improves inaccuracy by 70.5%, on average, compared with conventional techniques using ITC 99 and ISCAS 89 benchmark circuits when the enable probability is 1/3, while the runtime overhead is only 1.7% on average.","PeriodicalId":256879,"journal":{"name":"2015 IEEE 24th Asian Test Symposium (ATS)","volume":"6 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2015-11-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116709528","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

Fault Simulation and Test Pattern Generation for Cross-gate Defects in FinFET Circuits FinFET电路中栅极交叉缺陷的故障模拟与测试图生成

2015 IEEE 24th Asian Test Symposium (ATS) Pub Date : 2015-11-22 DOI: 10.1109/ATS.2015.38

Kuan-Ying Chiang, Yu-Hao Ho, Yo-Wei Chen, Cheng-Sheng Pan, C. Li

引用次数: 8