2009 IEEE/ACM International Conference on Computer-Aided Design - Digest of Technical Papers最新文献_第4页

REMiS: Run-time energy minimization scheme in a reconfigurable processor with dynamic power-gated instruction set REMiS:具有动态电源门控指令集的可重构处理器的运行时能量最小化方案

2009 IEEE/ACM International Conference on Computer-Aided Design - Digest of Technical Papers Pub Date : 2009-11-02 DOI: 10.1145/1687399.1687411

M. Shafique, L. Bauer, J. Henkel

{"title":"REMiS: Run-time energy minimization scheme in a reconfigurable processor with dynamic power-gated instruction set","authors":"M. Shafique, L. Bauer, J. Henkel","doi":"10.1145/1687399.1687411","DOIUrl":"https://doi.org/10.1145/1687399.1687411","url":null,"abstract":"Reconfigurable processors provide a means to flexible and energy-aware computing. In this paper, we present a new scheme for runtime energy minimization (REMiS) as part of a dynamically recon-figurable processor that is exposed to run-time varying constraints like performance and footprint (i.e. amount of reconfigurable fabric). The scheme chooses an energy-minimizing set of so-called Special Instructions (considering leakage, dynamic, and reconfiguration energy) and then 'power-gates' a temporarily unused subset of the Special Instruction set. We provide a comprehensive evaluation for different technologies (ranging from 65 nm to 150 nm) and thereby show that our scheme is technology independent, i.e. it is beneficial for various technologies alike. By means of an H.264 video encoder we demonstrate that for certain performance constraints our scheme (applied to our in-house reconfigurable processor) achieves an allover energy saving of up to 40.8% (avg. 24.8%) compared to a performance-maximizing scheme. We also demonstrate that our scheme is equally beneficial to various other state-of-the-art reconfigurable processor architectures like Molen where it achieves energy savings of up to 48.7% (avg. 28.93%) at 65 nm. We have employed an H.264 encoder within this paper as an application in order to demonstrate the strengths of our scheme, since the H.264's complexity and run-time unpredictability present a challenging scenario for state-of-the-art architectures.","PeriodicalId":256358,"journal":{"name":"2009 IEEE/ACM International Conference on Computer-Aided Design - Digest of Technical Papers","volume":"60 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2009-11-02","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115308002","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 25

Intrinsic NBTI-variability aware statistical pipeline performance assessment and tuning 内在的nbti可变性感知统计管道性能评估和调整

2009 IEEE/ACM International Conference on Computer-Aided Design - Digest of Technical Papers Pub Date : 2009-11-02 DOI: 10.1145/1687399.1687429

B. Vaidyanathan, A. Oates, Yuan Xie

引用次数: 12

Timing Arc based logic analysis for false noise reduction 基于时序弧的逻辑分析降噪方法

2009 IEEE/ACM International Conference on Computer-Aided Design - Digest of Technical Papers Pub Date : 2009-11-02 DOI: 10.1145/1687399.1687440

Murthy Palla, J. Bargfrede, Stephan Eggersglüß, W. Anheier, R. Drechsler

{"title":"Timing Arc based logic analysis for false noise reduction","authors":"Murthy Palla, J. Bargfrede, Stephan Eggersglüß, W. Anheier, R. Drechsler","doi":"10.1145/1687399.1687440","DOIUrl":"https://doi.org/10.1145/1687399.1687440","url":null,"abstract":"The problem of calculating accurate impact of crosstalk on a circuit considering its inherent logic and timing properties is very complex. Although it has been widely studied, it still lacks an efficient solution. As a result, state-of-the-art crosstalk calculators use simplistic and overly pessimistic models resulting in the over-estimation of crosstalk effects. Such pessimism in crosstalk analysis often leads to the triggering of false violations and consequently an inefficient use of design resources. The main contribution of this paper is a novel technique called Timing Arc Based Logic Analysis (TABLA) that serves as an efficient means to calculate realistic crosstalk bounds. TABLA uses timing arcs as basic elements to perform an efficient temporal logic analysis employing the min-max timing model using dedicated solvers for logic and timing. Additionally, a procedure to generate powerful conflict clauses is proposed to improve the run time of the overall analysis. The proposed technique has been tested in an industrial environment on benchmark circuits as well as on an industrial design, and results are provided.","PeriodicalId":256358,"journal":{"name":"2009 IEEE/ACM International Conference on Computer-Aided Design - Digest of Technical Papers","volume":"23 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2009-11-02","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127599966","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 4

GHM: A generalized Hamiltonian method for passivity test of impedance/admittance descriptor systems 阻抗/导纳广义系统无源性测试的广义哈密顿方法

2009 IEEE/ACM International Conference on Computer-Aided Design - Digest of Technical Papers Pub Date : 2009-11-02 DOI: 10.1145/1687399.1687541

Zheng Zhang, Chi-Un Lei, N. Wong

引用次数: 25

Voltage binning under process variation 工艺变化下的电压分束

2009 IEEE/ACM International Conference on Computer-Aided Design - Digest of Technical Papers Pub Date : 2009-11-02 DOI: 10.1145/1687399.1687480

V. Zolotov, C. Visweswariah, Jinjun Xiong

引用次数: 29

POWER7 — Verification challenge of a multi-core processor POWER7——多核处理器的验证挑战

2009 IEEE/ACM International Conference on Computer-Aided Design - Digest of Technical Papers Pub Date : 2009-11-02 DOI: 10.1145/1687399.1687551

Klaus-Dieter Schubert

{"title":"POWER7 — Verification challenge of a multi-core processor","authors":"Klaus-Dieter Schubert","doi":"10.1145/1687399.1687551","DOIUrl":"https://doi.org/10.1145/1687399.1687551","url":null,"abstract":"Over the years functional hardware verification has made significant progress in the areas of traditional simulation techniques, hardware accelerator usage and last but not least formal verification approaches. This has been sufficient to deal with the additional design content and complexity increase that has been happening at the same time. For POWER7, IBM's first high end 8-core microprocessor, these incremental improvements in verification have been deemed not to be enough by themselves, because the chip was not just a remap of an existing design with more cores. The infrastructure on the chip had to be changed significantly, while at the same time the business side requested a shorter development cycle with perfect quality but without growing the team. Looking at these constraints a two phase approach seemed to be the only solution. This paper commences with the highlights of the first phase, where improvements to the existing process have been identified. This includes topics ranging from enhanced test case generation, over advancements in structural checking to the extensions of the formal verification scope both in property checking and sequential equivalence checking. At the same time, the paper describes the second phase which has targeted the exploitation of synergy across the various verification activities. The active interlock between simulation, formal verification and the design has helped to reduce workload and improved the project schedule. And the usage of coverage in holistic way from unit level simulation to acceleration has led to new innovations and new insight, which improved the overall verification process. Finally, an outlook on future challenges and future trends is given. Categories and Subject Descriptors B.6.3 [Logic Design]: Design Aids — Verification. General Terms Verification","PeriodicalId":256358,"journal":{"name":"2009 IEEE/ACM International Conference on Computer-Aided Design - Digest of Technical Papers","volume":"58 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2009-11-02","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126665414","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 6

Parallel multi-level analytical global placement on graphics processing units 在图形处理单元上并行多级分析全局放置

2009 IEEE/ACM International Conference on Computer-Aided Design - Digest of Technical Papers Pub Date : 2009-11-02 DOI: 10.1145/1687399.1687525

J. Cong, Yi Zou

引用次数: 32

Computing quadratic approximations for the isochrons of oscillators: A general theory and advanced numerical methods 计算振荡器等时线的二次逼近:一般理论和先进的数值方法

2009 IEEE/ACM International Conference on Computer-Aided Design - Digest of Technical Papers Pub Date : 2009-11-02 DOI: 10.1145/1687399.1687475

O. Suvak, A. Demir

{"title":"Computing quadratic approximations for the isochrons of oscillators: A general theory and advanced numerical methods","authors":"O. Suvak, A. Demir","doi":"10.1145/1687399.1687475","DOIUrl":"https://doi.org/10.1145/1687399.1687475","url":null,"abstract":"We first review the notion of isochrons for oscillators, which has been developed and heavily utilized in mathematical biology in studying biological oscillations. Isochrons were instrumental in introducing a notion of generalized phase for an oscillation and form the basis for oscillator perturbation analysis formulations. Calculating the isochrons of an oscillator is a very difficult task. Except for some very simple planar oscillators, isochrons can not be calculated analytically and one has to resort to numerical techniques. Previously proposed numerical methods for computing isochrons can be regarded as brute-force, which become totally impractical for non-planar oscillators with dimension more than two. In this paper, we present a precise and carefully developed theory and advanced numerical techniques for computing local but quadratic approximations for isochrons. Previous work offers the theory and the numerical methods needed for computing only linear approximations for isochrons. Our treatment is general and applicable to oscillators with large dimension. We present examples for isochron computations, verify our results against exact calculations in a simple case, and allude to several applications among many where quadratic approximations of isochrons will be of use.","PeriodicalId":256358,"journal":{"name":"2009 IEEE/ACM International Conference on Computer-Aided Design - Digest of Technical Papers","volume":"274 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2009-11-02","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131671325","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 5

DynaTune: Circuit-level optimization for timing speculation considering dynamic path behavior 考虑动态路径行为的时序推测的电路级优化

2009 IEEE/ACM International Conference on Computer-Aided Design - Digest of Technical Papers Pub Date : 2009-11-02 DOI: 10.1145/1687399.1687430

Lu Wan, Deming Chen

{"title":"DynaTune: Circuit-level optimization for timing speculation considering dynamic path behavior","authors":"Lu Wan, Deming Chen","doi":"10.1145/1687399.1687430","DOIUrl":"https://doi.org/10.1145/1687399.1687430","url":null,"abstract":"Traditional circuit design focuses on optimizing the static critical paths no matter how infrequently these paths are exercised dynamically. Circuit optimization is then tuned to the worst-case conditions to guarantee error-free computation but may also lead to very inefficient designs. Recently, there are processor works that over-clock the chip to achieve higher performance to the point where timing errors occur, and then error correction is performed either through circuit-level or microarchitecture-level techniques. This approach in general is referred to as Timing Speculation. In this paper, we propose a new circuit optimization technique \"DynaTune\" for timing speculation based on the dynamic behavior of a circuit. DynaTune optimizes the most dynamically critical gates of a circuit and improves the circuit's throughput under a fixed power budget. We test this proposed technique with two timing speculation schemes — Telescopic Unit (TU) and Razor Logic (RZ). Experimental results show that applying DynaTune on the Leon3 processor can increase the throughput of critical modules by up to 13% and 20% compared to the timing-speculative and non-timing-speculative results optimized by Synopsys Design Compiler, respectively. For MCNC benchmark circuits, DynaTune combined with TU can provide 9% and 20% throughput gains on average compared to timing-speculative and non-timing-speculative results optimized by Design Compiler. When combined with RZ, DynaTune can achieve 8% and 15% throughput gains on average for above experiments. Categories and Subject Descriptors B.6.3 [Hardware]: Design Aids — Optimization. General Terms Algorithms, Performance, Design, Experimentation","PeriodicalId":256358,"journal":{"name":"2009 IEEE/ACM International Conference on Computer-Aided Design - Digest of Technical Papers","volume":"69 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2009-11-02","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130441392","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 53

Memory organization and data layout for instruction set extensions with architecturally visible storage 具有结构可见存储器的指令集扩展的存储器组织和数据布局

2009 IEEE/ACM International Conference on Computer-Aided Design - Digest of Technical Papers Pub Date : 2009-11-02 DOI: 10.1145/1687399.1687527

Panagiotis Athanasopoulos, P. Brisk, Y. Leblebici, P. Ienne

引用次数: 1