2009 IEEE/ACM International Conference on Computer-Aided Design - Digest of Technical Papers最新文献_第10页

Variability analysis of FinFET-based devices and circuits considering electrical confinement and width quantization 考虑电约束和宽度量化的基于finfet的器件和电路的可变性分析

2009 IEEE/ACM International Conference on Computer-Aided Design - Digest of Technical Papers Pub Date : 2009-11-02 DOI: 10.1145/1687399.1687495

S. H. Rasouli, K. Endo, K. Banerjee

{"title":"Variability analysis of FinFET-based devices and circuits considering electrical confinement and width quantization","authors":"S. H. Rasouli, K. Endo, K. Banerjee","doi":"10.1145/1687399.1687495","DOIUrl":"https://doi.org/10.1145/1687399.1687495","url":null,"abstract":"FinFET is considered as the most likely candidate to substitute bulk CMOS technology. FinFET-based design, however, requires special attention due to its exclusive properties such as width quantization and electrical confinement (quantum-mechanical effect) even in subthreshold regime. Considering these exclusive properties of FinFETs, the sources of process variations and their effects on FinFET-based circuit characteristics can be significantly different from that in bulk CMOS devices. This paper identifies a new source of random process variation due to the gate work-function variation and resulting electrical confinement in emerging high-k/metal-gate FinFET devices. In order to capture the effect of the variations on the characteristics of multifin FinFETs (considering their width quantization property), this paper also presents a new statistical framework to accurately predict the effective threshold voltage of multifin FinFET devices. This framework is subsequently used to predict the leakage profile of FinFET-based SRAM cells. Since FinFETs are optimal for ultra-low-voltage operations due to near-ideal subthreshold swing (60 mV/dec), we focus on FinFET-based SRAM (including subthreshold SRAM) design. Contrary to the low sensitivity of the static noise margin (SNM) to the width of the pull-down devices in bulk-CMOS subthreshold SRAMs, our analysis shows, for the first time, the significant impact of employing multifin pull-down devices on the SNM of subthreshold FinFET SRAMs.","PeriodicalId":256358,"journal":{"name":"2009 IEEE/ACM International Conference on Computer-Aided Design - Digest of Technical Papers","volume":"41 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2009-11-02","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123273931","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 20

Security against hardware Trojan through a novel application of design obfuscation 通过一种新颖的设计混淆应用来防范硬件木马

2009 IEEE/ACM International Conference on Computer-Aided Design - Digest of Technical Papers Pub Date : 2009-11-02 DOI: 10.1145/1687399.1687424

R. Chakraborty, S. Bhunia

引用次数: 185

Genetic design automation 基因设计自动化

2009 IEEE/ACM International Conference on Computer-Aided Design - Digest of Technical Papers Pub Date : 2009-11-02 DOI: 10.1145/1687399.1687531

C. Myers, Nathan A. Barker, Hiroyuki Kuwahara, K. R. Jones, C. Madsen, Nam-Phuong D. Nguyen

引用次数: 12

Retiming and time borrowing: Optimizing high-performance pulsed-latch-based circuits 重定时和时间借用:优化高性能脉冲锁存电路

2009 IEEE/ACM International Conference on Computer-Aided Design - Digest of Technical Papers Pub Date : 2009-11-02 DOI: 10.1145/1687399.1687471

Seonggwan Lee, Seungwhun Paik, Youngsoo Shin

引用次数: 18

Characterizing within-die variation from multiple supply port IDDQ measurements 从多个电源端口IDDQ测量中表征模内变化

2009 IEEE/ACM International Conference on Computer-Aided Design - Digest of Technical Papers Pub Date : 2009-11-02 DOI: 10.1145/1687399.1687479

K. Agarwal, D. Acharyya, J. Plusquellic

引用次数: 3

Temporal and spatial idleness exploitation for optimal-grained leakage control 利用时间和空间空闲进行最佳粒度泄漏控制

2009 IEEE/ACM International Conference on Computer-Aided Design - Digest of Technical Papers Pub Date : 2009-11-02 DOI: 10.1145/1687399.1687487

Hao Xu, R. Vemuri, W. Jone

引用次数: 7

CROP: Fast and effective congestion refinement of placement CROP:快速有效的拥堵定位细化

2009 IEEE/ACM International Conference on Computer-Aided Design - Digest of Technical Papers Pub Date : 2009-11-02 DOI: 10.1145/1687399.1687465

Yanheng Zhang, C. Chu

{"title":"CROP: Fast and effective congestion refinement of placement","authors":"Yanheng Zhang, C. Chu","doi":"10.1145/1687399.1687465","DOIUrl":"https://doi.org/10.1145/1687399.1687465","url":null,"abstract":"Modern circuits become harder to route with the ever decreasing design features. Previous routability-driven placement techniques are usually tightly coupled with the underlying placers. So usually they cannot be easily integrated into various placement tools. In this paper, we propose a tool called CROP (Congestion Refinement of Placement) for mixed-size placement solutions. CROP is independent of any placer. It takes a legalized placement solution and then relocates the modules to improve routability without significantly disturbing the original placement solution. CROP interleaves a congestion-driven module shifting technique and a congestion-driven detailed placement technique. Basically the shifting technique targets at better allocating the routing resources. Shifting in each direction can be formulated as a linear program (LP) for resizing each G-Cell. Instead of solving the computationally expensive LP, we discover that the LP formulation could be relaxed and solved by a very efficient longest-path computation. Then the congestion-driven detailed placement technique is proposed to better distribute the routing demands. Congestion reduction is realized by weighting the HPWL with congestion coefficient during detailed placement. The experimental results show that CROP is capable of effectively alleviating the congestion for unroutable placement solutions. We apply it to placement solutions generated by four different placers on the ISPD05/06 placement benchmarks [1] [2]. Within a very short runtime, CROP greatly improves the routability and saves execution time for the routing stage after refinement.","PeriodicalId":256358,"journal":{"name":"2009 IEEE/ACM International Conference on Computer-Aided Design - Digest of Technical Papers","volume":"131 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2009-11-02","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131071949","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 40

Final-value ODEs: Stable numerical integration and its application to parallel circuit analysis 终值ode:稳定数值积分及其在并行电路分析中的应用

2009 IEEE/ACM International Conference on Computer-Aided Design - Digest of Technical Papers Pub Date : 2009-11-02 DOI: 10.1145/1687399.1687476

Wei Dong, Peng Li

{"title":"Final-value ODEs: Stable numerical integration and its application to parallel circuit analysis","authors":"Wei Dong, Peng Li","doi":"10.1145/1687399.1687476","DOIUrl":"https://doi.org/10.1145/1687399.1687476","url":null,"abstract":"While solving initial-value ODEs is the de facto approach to time-domain circuit simulation, the opposite act, solving final-value ODEs, has been neglected for a long time. Stable numerical integration of initial-value ODEs involves significant complications; the application of standard integration methods simply leads to instability. We show that not only practically meaningful applications of final-value ODE problems exist, but also the inherent stability challenges may be addressed by recently proposed numerical methods. Furthermore, we demonstrate an elegant bi-directional parallel circuit simulation scheme, where one time-domain simulation task is sped up by simultaneously solving initial and final-value ODEs, one from each end of the time axis. The proposed approach has unique and favorable properties: the solutions of the two ODE problems are completely data independent with built-in automatic load balancing. As a specific application study, we demonstrate the proposed technique under the contexts of parallel digital timing simulation and the shooting-Newton based steady-state analysis. Categories and Subject Descriptors B.7.2 [Integrated Circuits]: Design Aids-simulation General Terms Algorithms, Design, Performance","PeriodicalId":256358,"journal":{"name":"2009 IEEE/ACM International Conference on Computer-Aided Design - Digest of Technical Papers","volume":"7 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2009-11-02","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131508363","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 6

An elegant hardware-corroborated statistical repair and test methodology for conquering aging effects 一种优雅的硬件证实的统计修复和测试方法，用于征服老化效应

2009 IEEE/ACM International Conference on Computer-Aided Design - Digest of Technical Papers Pub Date : 2009-11-02 DOI: 10.1145/1687399.1687494

R. Kanj, R. Joshi, C. Adams, J. Warnock, S. Nassif

引用次数: 14

Layout-dependent STI stress analysis and stress-aware RF/analog circuit design optimization 依赖于布图的STI应力分析和应力感知RF/模拟电路设计优化

2009 IEEE/ACM International Conference on Computer-Aided Design - Digest of Technical Papers Pub Date : 2009-11-02 DOI: 10.1145/1687399.1687497

Jiying Xue, Zuochang Ye, Yangdong Deng, Hongrui Wang, Liu Yang, Zhiping Yu

引用次数: 20