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Thermal modeling for 3D-ICs with integrated microchannel cooling 集成微通道冷却的3d集成电路热建模
2009 IEEE/ACM International Conference on Computer-Aided Design - Digest of Technical Papers Pub Date : 2009-11-02 DOI: 10.1145/1687399.1687447
H. Mizunuma, Chia-Lin Yang, Yi-Chang Lu
{"title":"Thermal modeling for 3D-ICs with integrated microchannel cooling","authors":"H. Mizunuma, Chia-Lin Yang, Yi-Chang Lu","doi":"10.1145/1687399.1687447","DOIUrl":"https://doi.org/10.1145/1687399.1687447","url":null,"abstract":"Integrated microchannel liquid-cooling technology is envisioned as a viable solution to alleviate an increasing thermal stress imposed by 3D stacked ICs. Thermal modeling for microchannel cooling is challenging due to its complicated thermal-wake effect, a localized temperature wake phenomenon downstream of a heated source in the flow. This paper presents a fast and accurate thermal-wake aware thermal model for integrated microchannel 3D ICs. Validation results show the proposed thermal model achieves more than 400× speed up and only 2.0% error in comparison with a commercial numerical simulation tool. We also demonstrate the use of the proposed thermal model for thermal optimization during the IC placement stage. We find that due to the thermal-wake effect, tiles are placed in the descending order of power magnitude along the flow direction. We also find that modeling thermal-wakes is critical for generating a thermal-aware placement for integrated microchannel-cooled 3D IC. It could result in up to 25°C peak temperature difference according to our experiments.","PeriodicalId":256358,"journal":{"name":"2009 IEEE/ACM International Conference on Computer-Aided Design - Digest of Technical Papers","volume":"33 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2009-11-02","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127353681","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 56
Global routing revisited 重新审视全局路由
2009 IEEE/ACM International Conference on Computer-Aided Design - Digest of Technical Papers Pub Date : 2009-11-02 DOI: 10.1145/1687399.1687549
Michael D. Moffitt
{"title":"Global routing revisited","authors":"Michael D. Moffitt","doi":"10.1145/1687399.1687549","DOIUrl":"https://doi.org/10.1145/1687399.1687549","url":null,"abstract":"Recent progress in the area of global routing has been remarkable; yet, in many ways, the classical formulation has yet to catch up with the demands imposed by modern physical synthesis flows. In this work, we visit (and revisit) the topic of global routing. We provide a brief review of global routing's history, and touch on recent work that has contributed to the state-of-the-art in the field. While we cover in depth the basic principles behind leading approaches, we also emphasize open challenges and problems that remain unresolved. We argue that not only does the current academic formulation lack key components of the true routing problem - such as scenic control, layer directives, and capabilities for integration with physical synthesis - but also that present methods are likely to fail when extended toward the more generalized formulation. Finally, we offer a revised incarnation of the ISPD benchmarks to encourage continued progress in the research community.","PeriodicalId":256358,"journal":{"name":"2009 IEEE/ACM International Conference on Computer-Aided Design - Digest of Technical Papers","volume":"12 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2009-11-02","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125417087","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 20
A rigorous framework for convergent net weighting schemes in timing-driven placement 时序驱动布局中收敛净加权方案的严格框架
2009 IEEE/ACM International Conference on Computer-Aided Design - Digest of Technical Papers Pub Date : 2009-11-02 DOI: 10.1145/1687399.1687454
T. Chan, J. Cong, Eric Radke
{"title":"A rigorous framework for convergent net weighting schemes in timing-driven placement","authors":"T. Chan, J. Cong, Eric Radke","doi":"10.1145/1687399.1687454","DOIUrl":"https://doi.org/10.1145/1687399.1687454","url":null,"abstract":"We present a rigorous framework that defines a class of net weighting schemes in which unconstrained minimization is successively performed on a weighted objective. We show that, provided certain goals are met in the unconstrained minimization, these net weighting schemes are guaranteed to converge to the optimal solution of the original timing-constrained placement problem. These are the first results that provide conditions under which a net weighting scheme will converge to a timing optimal placement. We then identify several weighting schemes that satisfy the given convergence properties and implement them, with promising results: a modification of the weighting scheme given in results in consistently improved delay over the original, 4% on average, without increase in computation time.","PeriodicalId":256358,"journal":{"name":"2009 IEEE/ACM International Conference on Computer-Aided Design - Digest of Technical Papers","volume":"31 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2009-11-02","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116819103","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 14
Virtual probe: A statistically optimal framework for minimum-cost silicon characterization of nanoscale integrated circuits 虚拟探针:用于纳米级集成电路的最低成本硅表征的统计优化框架
2009 IEEE/ACM International Conference on Computer-Aided Design - Digest of Technical Papers Pub Date : 2009-11-02 DOI: 10.1145/1687399.1687481
Xin Li, Rob A. Rutenbar, R. D. Blanton
{"title":"Virtual probe: A statistically optimal framework for minimum-cost silicon characterization of nanoscale integrated circuits","authors":"Xin Li, Rob A. Rutenbar, R. D. Blanton","doi":"10.1145/1687399.1687481","DOIUrl":"https://doi.org/10.1145/1687399.1687481","url":null,"abstract":"In this paper, we propose a new technique, referred to as virtual probe (VP), to efficiently measure, characterize and monitor both inter-die and spatially-correlated intra-die variations in nanoscale manufacturing process. VP exploits recent breakthroughs in compressed sensing [15]-[17] to accurately predict spatial variations from an exceptionally small set of measurement data, thereby reducing the cost of silicon characterization. By exploring the underlying sparse structure in (spatial) frequency domain, VP achieves substantially lower sampling frequency than the well-known (spatial) Nyquist rate. In addition, VP is formulated as a linear programming problem and, therefore, can be solved both robustly and efficiently. Our industrial measurement data demonstrate that by testing the delay of just 50 chips on a wafer, VP accurately predicts the delay of the other 219 chips on the same wafer. In this example, VP reduces the estimation error by up to 10× compared to other traditional methods. Categories and Subject Descriptors B.7.2 [Integrated Circuits]: Design Aids — Verification General Terms Algorithms","PeriodicalId":256358,"journal":{"name":"2009 IEEE/ACM International Conference on Computer-Aided Design - Digest of Technical Papers","volume":"16 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2009-11-02","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129029716","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 51
Energy reduction for STT-RAM using early write termination 使用提前写终止减少STT-RAM的能量
2009 IEEE/ACM International Conference on Computer-Aided Design - Digest of Technical Papers Pub Date : 2009-11-02 DOI: 10.1145/1687399.1687448
Ping Zhou, Bo Zhao, Jun Yang, Youtao Zhang
{"title":"Energy reduction for STT-RAM using early write termination","authors":"Ping Zhou, Bo Zhao, Jun Yang, Youtao Zhang","doi":"10.1145/1687399.1687448","DOIUrl":"https://doi.org/10.1145/1687399.1687448","url":null,"abstract":"The emerging Spin Torque Transfer memory (STT-RAM) is a promising candidate for future on-chip caches due to STT-RAM's high density, low leakage, long endurance and high access speed. However, one of the major challenges of STT-RAM is its high write current, which is disadvantageous when used as an on-chip cache since the dynamic power generated is too high. In this paper, we propose Early Write Termination (EWT), a novel technique to significantly reduce write energy with no performance penalty. EWT can be implemented with low complexity and low energy overhead. Our evaluation shows that up to 80% of write energy reduction can be achieved through EWT, resulting 33% less total energy consumption, and 34% reduction in ED2. These results indicate that EWT is an effective and practical scheme to improve the energy efficiency of a STT-RAM cache.","PeriodicalId":256358,"journal":{"name":"2009 IEEE/ACM International Conference on Computer-Aided Design - Digest of Technical Papers","volume":"7 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2009-11-02","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121394943","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 337
A study of Through-Silicon-Via impact on the 3D stacked IC layout 通硅通孔对3D堆叠IC布局影响的研究
2009 IEEE/ACM International Conference on Computer-Aided Design - Digest of Technical Papers Pub Date : 2009-11-02 DOI: 10.1145/1687399.1687524
Daehyun Kim, K. Athikulwongse, S. Lim
{"title":"A study of Through-Silicon-Via impact on the 3D stacked IC layout","authors":"Daehyun Kim, K. Athikulwongse, S. Lim","doi":"10.1145/1687399.1687524","DOIUrl":"https://doi.org/10.1145/1687399.1687524","url":null,"abstract":"Through-Silicon-Via (TSV) is the enabling technology for the finegrained 3D integration of multiple dies into a single stack. These TSVs occupy non-negligible silicon area because of their sheer size. This significant silicon area occupied by the TSVs and the interconnections made to the TSVs greatly affect area, power, performance, and reliability of 3D IC layouts. Well-managed TSVs alleviate congestion, reduce wirelength, and improve performance, whereas excessive TSVs not only increase the die area, but also have negative impact on many design objectives. In this paper, we study the impact of TSV on various aspects of 3D layouts. We use GDSII layouts of 2D and 3D designs, and thoroughly compare the pros and cons of TSV usage. We propose a new force-directed 3D gate-level placement that efficiently handles TSVs. In addition, we present an algorithm that assigns TSVs to nets to complete routing that involves TSVs. This algorithm, together with our 3D placer, is integrated into a commercial P&R tool to generate fully validated GDSII layouts. Our experiments based on synthesized benchmarks indicate that our algorithms help generate GDSII layouts of 3D designs that are optimized in terms of area, wirelength, and metal layer count.","PeriodicalId":256358,"journal":{"name":"2009 IEEE/ACM International Conference on Computer-Aided Design - Digest of Technical Papers","volume":"2017 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2009-11-02","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128184960","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 210
Yield estimation of SRAM circuits using “Virtual SRAM Fab” 基于“虚拟SRAM Fab”的SRAM电路良率估计
2009 IEEE/ACM International Conference on Computer-Aided Design - Digest of Technical Papers Pub Date : 2009-11-02 DOI: 10.1145/1687399.1687516
A. Bansal, Rama N. Singh, R. Kanj, S. Mukhopadhyay, Jin-fuw Lee, E. Acar, Amith Singhee, Keunwoo Kim, C. Chuang, S. Nassif, Fook-Luen Heng, K. Das
{"title":"Yield estimation of SRAM circuits using “Virtual SRAM Fab”","authors":"A. Bansal, Rama N. Singh, R. Kanj, S. Mukhopadhyay, Jin-fuw Lee, E. Acar, Amith Singhee, Keunwoo Kim, C. Chuang, S. Nassif, Fook-Luen Heng, K. Das","doi":"10.1145/1687399.1687516","DOIUrl":"https://doi.org/10.1145/1687399.1687516","url":null,"abstract":"Static Random Access Memories (SRAMs) are key components of modern VLSI designs and a major bottleneck to technology scaling as they use the smallest size devices with high sensitivity to manufacturing details. Analysis performed at the “schematic” level can be deceiving as it ignores the interdependence between the implementation layout and the resulting electrical performance. We present a computational framework, referred to as “Virtual SRAM Fab”, for analyzing and estimating pre-Si SRAM array manufacturing yield considering both lithographic and electrical variations. The framework is being demonstrated for SRAM design/optimization in 45nm nodes and currently being used for both 32nm and 22nm technology nodes. The application and merit of the framework are illustrated using two different SRAM cells in a 45nm PD/SOI technology, which have been designed for similar stability/performance, but exhibit different parametric yields due to layout/lithographic variations. We also demonstrate the application of Virtual SRAM Fab for prediction of layout-induced imbalance in an 8T cell, which is a popular candidate for SRAM implementation in 32–22nm technology nodes.","PeriodicalId":256358,"journal":{"name":"2009 IEEE/ACM International Conference on Computer-Aided Design - Digest of Technical Papers","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2009-11-02","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131503745","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 12
Resilient circuits — Enabling energy-efficient performance and reliability 弹性电路-实现节能性能和可靠性
2009 IEEE/ACM International Conference on Computer-Aided Design - Digest of Technical Papers Pub Date : 2009-11-02 DOI: 10.1145/1687399.1687414
J. Tschanz, K. Bowman, C. Wilkerson, Shih-Lien Lu, T. Karnik
{"title":"Resilient circuits — Enabling energy-efficient performance and reliability","authors":"J. Tschanz, K. Bowman, C. Wilkerson, Shih-Lien Lu, T. Karnik","doi":"10.1145/1687399.1687414","DOIUrl":"https://doi.org/10.1145/1687399.1687414","url":null,"abstract":"Voltage and frequency margins necessary to ensure correct processor operation under dynamic voltage, temperature, and aging variations result in performance and power overheads. Resilient circuit techniques, including embedded error-detection sequentials and tunable replica circuits, allow these margins to be reduced or eliminated, resulting in reliable, energy-efficient operation. Categories and Subject Descriptors B.7.1 [Integrated Circuits]: Types and design styles General Terms Performance, Design, Reliability","PeriodicalId":256358,"journal":{"name":"2009 IEEE/ACM International Conference on Computer-Aided Design - Digest of Technical Papers","volume":"310 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2009-11-02","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131818373","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 33
A circuit-software co-design approach for improving EDP in reconfigurable frameworks 改进可重构框架中EDP的电路-软件协同设计方法
2009 IEEE/ACM International Conference on Computer-Aided Design - Digest of Technical Papers Pub Date : 2009-11-02 DOI: 10.1145/1687399.1687423
Somnath Paul, S. Chatterjee, S. Mukhopadhyay, S. Bhunia
{"title":"A circuit-software co-design approach for improving EDP in reconfigurable frameworks","authors":"Somnath Paul, S. Chatterjee, S. Mukhopadhyay, S. Bhunia","doi":"10.1145/1687399.1687423","DOIUrl":"https://doi.org/10.1145/1687399.1687423","url":null,"abstract":"Use of two-dimensional memory array for lookup table (LUT) based reconfigurable computing frameworks has been proposed earlier for improvement in performance and energy-delay product (EDP). In this paper, we propose an integrated solution for achieving significantly higher EDP in these frameworks by leveraging on the read-dominant memory access pattern. First, we propose to employ an asymmetric memory cell design, which provides higher read performance (~2X) and lower read power (~1.6X) in order to improve the overall EDP during operation. Exploiting the fact that the proposed memory cell provides better read power/performance for cells storing logic `0', next we propose a content-aware application mapping approach, which tries to maximize the logic `0' content in the LUTs. We show that the joint circuit and application mapping level optimization approach provides significant improvement in system EDP for a set of benchmark circuits.","PeriodicalId":256358,"journal":{"name":"2009 IEEE/ACM International Conference on Computer-Aided Design - Digest of Technical Papers","volume":"287 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2009-11-02","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132584761","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 9
An accurate and efficient performance analysis approach based on queuing model for network on chip 基于排队模型的片上网络准确高效的性能分析方法
2009 IEEE/ACM International Conference on Computer-Aided Design - Digest of Technical Papers Pub Date : 2009-11-02 DOI: 10.1145/1687399.1687505
Ming-che Lai, L. Gao, Nong Xiao, Zhiying Wang
{"title":"An accurate and efficient performance analysis approach based on queuing model for network on chip","authors":"Ming-che Lai, L. Gao, Nong Xiao, Zhiying Wang","doi":"10.1145/1687399.1687505","DOIUrl":"https://doi.org/10.1145/1687399.1687505","url":null,"abstract":"An accurate and highly-efficient performance analysis approach is extremely important for the early-stage designs of network-on-chip. In this paper, the novel M/G/1/N queuing models for generic routers are proposed to analyze various packet blockings and then the performance analysis algorithm is presented to estimate some key metrics in terms of packet latency, buffer utilization, etc. For single-channel and multi-channel routers, the comparisons between analysis and observed results validate that the proposed approach with mean errors of 6.9% and 7.8% achieve the speed-ups of 240 and 210 times respectively. In our design methodology, this approach can not only effectively direct NoC synthesis process but also be conveniently applied to multi-objective optimizations to find the best mapping solutions. Categories and Subject Descriptors: B.4.3 [Hardware]: Input/Output and Data Communication-Interconnections. General Terms: Algorithms, Performance.","PeriodicalId":256358,"journal":{"name":"2009 IEEE/ACM International Conference on Computer-Aided Design - Digest of Technical Papers","volume":"125 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2009-11-02","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115357932","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 30
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