2009 IEEE/ACM International Conference on Computer-Aided Design - Digest of Technical Papers最新文献_第2页

Energy-optimal dynamic thermal management for green computing 绿色计算的能量优化动态热管理

2009 IEEE/ACM International Conference on Computer-Aided Design - Digest of Technical Papers Pub Date : 2009-11-02 DOI: 10.1145/1687399.1687520

Donghwa Shin, Jihun Kim, N. Chang, J. Choi, S. Chung, Eui-Young Chung

引用次数: 36

Timing model extraction for sequential circuits considering process variations 考虑过程变化的时序电路时序模型提取

2009 IEEE/ACM International Conference on Computer-Aided Design - Digest of Technical Papers Pub Date : 2009-11-02 DOI: 10.1145/1687399.1687463

Bing Li, Ning Chen, Ulf Schlichtmann

{"title":"Timing model extraction for sequential circuits considering process variations","authors":"Bing Li, Ning Chen, Ulf Schlichtmann","doi":"10.1145/1687399.1687463","DOIUrl":"https://doi.org/10.1145/1687399.1687463","url":null,"abstract":"As semiconductor devices continue to scale down, process variations become more relevant for circuit design. Facing such variations, statistical static timing analysis is introduced to model variations more accurately so that the pessimism in traditional worst case timing analysis is reduced. Because all delays are modeled using correlated random variables, most statistical timing methods are much slower than corner based timing analysis. To speed up statistical timing analysis, we propose a method to extract timing models for flip-flop and latch based sequential circuits respectively. When such a circuit is used as a module in a hierarchical design, the timing model instead of the original circuit is used for timing analysis. The extracted timing models are much smaller than the original circuits. Experiments show that using extracted timing models accelerates timing verification by orders of magnitude compared to previous approaches using flat netlists directly. Accuracy is maintained, however, with the mean and standard deviation of the clock period both showing usually less than 1% error compared to Monte Carlo simulation on a number of benchmark circuits.","PeriodicalId":256358,"journal":{"name":"2009 IEEE/ACM International Conference on Computer-Aided Design - Digest of Technical Papers","volume":"16 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2009-11-02","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"117031250","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 4

MOLES: Malicious off-chip leakage enabled by side-channels 痣:由侧通道启用的恶意芯片外泄漏

2009 IEEE/ACM International Conference on Computer-Aided Design - Digest of Technical Papers Pub Date : 2009-11-02 DOI: 10.1145/1687399.1687425

Lang Lin, W. Burleson, C. Paar

{"title":"MOLES: Malicious off-chip leakage enabled by side-channels","authors":"Lang Lin, W. Burleson, C. Paar","doi":"10.1145/1687399.1687425","DOIUrl":"https://doi.org/10.1145/1687399.1687425","url":null,"abstract":"Economic incentives have driven the semiconductor industry to separate design from fabrication in recent years. This trend leads to potential vulnerabilities from untrusted circuit foundries to covertly implant malicious hardware Trojans into a genuine design. Hardware Trojans provide back doors for on-chip manipulation, or leak secret information off-chip once the compromised IC is deployed in the field. This paper explores the design space of hardware Trojans and proposes a novel technique, “Malicious Off-chip Leakage Enabled by Side-channels” (MOLES), which employs power side-channels to convey secret information off-chip. An experimental MOLES circuit is designed with fewer than 50 gates and is embedded into an Advanced Encryption Standard (AES) cryptographic circuit in a predictive 45nm CMOS technology model. Engineered by a spread-spectrum technique, the MOLES technique is capable of leaking multi-bit information below the noise power level of the host IC to evade evaluators' detections. In addition, a generalized methodology for a class of MOLES circuits and design verification by statistical correlation analysis are presented. The goal of this work is to demonstrate the potential threats of MOLES on embedded system security. Nevertheless, MOLES could be constructively used for hardware authentication, fingerprinting and IP protection.","PeriodicalId":256358,"journal":{"name":"2009 IEEE/ACM International Conference on Computer-Aided Design - Digest of Technical Papers","volume":"20 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2009-11-02","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"117249330","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 140

CRISP: Congestion reduction by iterated spreading during placement CRISP:在放置期间通过迭代传播减少拥塞

2009 IEEE/ACM International Conference on Computer-Aided Design - Digest of Technical Papers Pub Date : 2009-11-02 DOI: 10.1145/1687399.1687467

Jarrod A. Roy, Natarajan Viswanathan, Gi-Joon Nam, C. Alpert, I. Markov

引用次数: 54

Multi-level clustering for clock skew optimization 时钟倾斜优化的多级聚类

2009 IEEE/ACM International Conference on Computer-Aided Design - Digest of Technical Papers Pub Date : 2009-11-02 DOI: 10.1145/1687399.1687502

J. Casanova, J. Cortadella

引用次数: 10

Leveraging efficient parallel pattern search for clock mesh optimization 利用高效并行模式搜索时钟网格优化

2009 IEEE/ACM International Conference on Computer-Aided Design - Digest of Technical Papers Pub Date : 2009-11-02 DOI: 10.1145/1687399.1687499

Xiaoji Ye, S. Narasimhan, Peng Li

{"title":"Leveraging efficient parallel pattern search for clock mesh optimization","authors":"Xiaoji Ye, S. Narasimhan, Peng Li","doi":"10.1145/1687399.1687499","DOIUrl":"https://doi.org/10.1145/1687399.1687499","url":null,"abstract":"Mesh-based clock distribution network has been employed in many high-performance microprocessor designs due to its favorable properties such as low clock skew and robustness. Such clock distributions are usually highly complex. While the simulation of clock meshes is already time consuming, tuning such networks under tight performance constraints is a more daunting task. In this paper, we address the challenging task of driver size optimization with a goal of skew minimization. The expensive objective function evaluations and difficulty in getting explicit sensitivity information make this problem intractable to standard optimization methods. We propose to explore the recently developed asynchronous parallel pattern search (APPS) method for efficient driver size tuning. While being a search-based method, APPS not only provides the desirable derivative-free optimization capability, but is also amenable to parallelization and possesses appealing theoretically rigorous convergence properties. We show how such a method can lead to powerful parallel sizing optimization of large clock meshes with significant runtime and quality advantages over the traditional sequential quadratic programming (SQP) method. We also show how design-specific properties and speeding-up techniques can be exploited to make the optimization even more efficient while maintaining the convergence of APPS in a practical sense.","PeriodicalId":256358,"journal":{"name":"2009 IEEE/ACM International Conference on Computer-Aided Design - Digest of Technical Papers","volume":"11 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2009-11-02","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128809228","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 3

Fast and reliable passivity assessment and enforcement with extended Hamiltonian pencil 快速和可靠的被动评估和执行与扩展哈密顿铅笔

2009 IEEE/ACM International Conference on Computer-Aided Design - Digest of Technical Papers Pub Date : 2009-11-02 DOI: 10.1145/1687399.1687542

Zuochang Ye, L. M. Silveira, J. Phillips

引用次数: 17

Gene-regulatory memories: Electrical-equivalent modeling, simulation and parameter identification 基因调控记忆:电等效建模、仿真和参数识别

2009 IEEE/ACM International Conference on Computer-Aided Design - Digest of Technical Papers Pub Date : 2009-11-02 DOI: 10.1145/1687399.1687492

Yong Zhang, Peng Li

{"title":"Gene-regulatory memories: Electrical-equivalent modeling, simulation and parameter identification","authors":"Yong Zhang, Peng Li","doi":"10.1145/1687399.1687492","DOIUrl":"https://doi.org/10.1145/1687399.1687492","url":null,"abstract":"The development of gene-regulatory memory circuits provides key understandings of biological information storage and enables new biological applications. Computer models and simulations can provide quantitative analysis and prediction of the behaviors and functions of genetic networks, thereby providing valuable verification and design guidance. In this paper, we model the nonlinear dynamics associated with various chemical reactions in gene-regulatory memory networks using chemical reaction equations. These reaction equations are mapped into a set of electrical-equivalent models and the network is simulated by an extended SPICE-like circuit simulation environment. Furthermore, we address the practical difficulty in direct characterization of network model parameters by developing a simulation-driven Bayesian framework for parameter identification. To ensure the reliable identification of key system properties, we propose a two-step structure-preserving parameter identification approach. The first step infers bistability, the most critical characteristics of a memory device; and the second step is geared towards identifying dynamical properties of the network while maintaining the identified bistability. We demonstrate the proposed approaches through extensive simulations that well agree with established biological understandings and identified networks that recreate measured circuit responses in a statistical sense.","PeriodicalId":256358,"journal":{"name":"2009 IEEE/ACM International Conference on Computer-Aided Design - Digest of Technical Papers","volume":"9 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2009-11-02","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127595832","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 5

A method for calculating hard QoS guarantees for Networks-on-Chip 一种计算片上网络硬QoS保证的方法

2009 IEEE/ACM International Conference on Computer-Aided Design - Digest of Technical Papers Pub Date : 2009-11-02 DOI: 10.1145/1687399.1687507

Dara Rahmati, S. Murali, L. Benini, F. Angiolini, G. Micheli, H. Sarbazi-Azad

引用次数: 29

Pre-ATPG path selection for near optimal post-ATPG process space coverage 为接近最优的atpg后进程空间覆盖率选择atpg前路径

2009 IEEE/ACM International Conference on Computer-Aided Design - Digest of Technical Papers Pub Date : 2009-11-02 DOI: 10.1145/1687399.1687419

Jiniun Xionq, Yiyu Shi, V. Zolotov, C. Visweswariah

{"title":"Pre-ATPG path selection for near optimal post-ATPG process space coverage","authors":"Jiniun Xionq, Yiyu Shi, V. Zolotov, C. Visweswariah","doi":"10.1145/1687399.1687419","DOIUrl":"https://doi.org/10.1145/1687399.1687419","url":null,"abstract":"Path delay testing is becoming increasingly important for high-performance chip testing in the presence of process variation. To guarantee full process space coverage, the ensemble of critical paths of all chips irrespective of their manufacturing process conditions needs to be tested, as different chips may have different critical paths. Existing coverage-based path selection techniques, however, suffer from the loss of coverage after ATPG (automatic test pattern generation), i.e., although the pre-ATPG path selection achieves good coverage, after ATPG, the coverage can be severely reduced as many paths turn out to be unsensitizable. This paper presents a novel path selection algorithm that, without running ATPG, selects a set of n paths to achieve near optimal post-ATPG coverage. Details of the algorithm and its optimality conditions are discussed. Experimental results show that, compared to the state-of-the-art, the proposed algorithm achieves not only superior post-ATPG coverage, but also significant runtime speedup. Categories and Subject Descriptors B.7.2 [Integrated Circuits]: Design Aids General Terms Algorithms, Design, Theory","PeriodicalId":256358,"journal":{"name":"2009 IEEE/ACM International Conference on Computer-Aided Design - Digest of Technical Papers","volume":"165 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2009-11-02","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116053152","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 12