2009 IEEE/ACM International Conference on Computer-Aided Design - Digest of Technical Papers最新文献_第5页

Nonvolatile memristor memory: Device characteristics and design implications 非易失性忆阻器存储器：器件特性和设计影响

2009 IEEE/ACM International Conference on Computer-Aided Design - Digest of Technical Papers Pub Date : 2009-11-02 DOI: 10.1145/1687399.1687491

Y. Ho, Garng M. Huang, Peng Li

引用次数: 289

Resilience in computer systems and networks 计算机系统和网络的弹性

2009 IEEE/ACM International Conference on Computer-Aided Design - Digest of Technical Papers Pub Date : 2009-11-02 DOI: 10.1145/1687399.1687415

Kishor S. Trivedi, Dong Seong Kim, R. Ghosh

引用次数: 71

Compacting test vector sets via strategic use of implications 通过有策略地使用隐含来压缩测试向量集

2009 IEEE/ACM International Conference on Computer-Aided Design - Digest of Technical Papers Pub Date : 2009-11-02 DOI: 10.1145/1687399.1687418

N. Alves, Jennifer Dworak, R. I. Bahar, Kundan Nepal

引用次数: 10

Decoupling capacitance efficient placement for reducing transient power supply noise 去耦电容高效放置，降低暂态电源噪声

2009 IEEE/ACM International Conference on Computer-Aided Design - Digest of Technical Papers Pub Date : 2009-11-02 DOI: 10.1145/1687399.1687538

Xiaoyi Wang, Yici Cai, Qiang Zhou, S. Tan, T. Eguia

{"title":"Decoupling capacitance efficient placement for reducing transient power supply noise","authors":"Xiaoyi Wang, Yici Cai, Qiang Zhou, S. Tan, T. Eguia","doi":"10.1145/1687399.1687538","DOIUrl":"https://doi.org/10.1145/1687399.1687538","url":null,"abstract":"Decoupling capacitance (decap) is an efficient way to reduce transient noise in on-chip power supply networks. However, excessive decap may cause more leakage power, chip resource waste, and even lead to more design iterations. In this paper, we present a novel decap-efficient placement algorithm for transient power supply noise reduction. In contrast to traditional design flow, our approach considers decap impacts at the placement stage to seek the placement minimizing decap requirements while still satisfying the traditional placement objectives. In the new method, we first devise a fast procedure to assess the decap requirement for the force-based placement framework, in which the required decap is modeled as a density function over the chip. Then, we build a corresponding supply and demand system to adjust the placement in favor of minimizing decap. Finally, we develop a decap efficient placement algorithm with a new force induced by imbalance between power supply and power demands. Experimental results show that the new combined placement and decap optimization flow could reduce the minimum decap area by 35% with a wire length increase of only 0.5% at nearly the same computational cost, which is efficient for practical problems.","PeriodicalId":256358,"journal":{"name":"2009 IEEE/ACM International Conference on Computer-Aided Design - Digest of Technical Papers","volume":"202 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2009-11-02","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124206082","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 4

Interpolating functions from large Boolean relations 从大布尔关系插值函数

2009 IEEE/ACM International Conference on Computer-Aided Design - Digest of Technical Papers Pub Date : 2009-11-02 DOI: 10.1145/1687399.1687544

J. H. Jiang, Hsuan-Po Lin, W. Hung

引用次数: 43

A parallel preconditioning strategy for efficient transistor-level circuit simulation 一种高效晶体管级电路仿真的并行预处理策略

2009 IEEE/ACM International Conference on Computer-Aided Design - Digest of Technical Papers Pub Date : 2009-11-02 DOI: 10.1145/1687399.1687477

H. Thornquist, E. Keiter, R. Hoekstra, D. Day, E. Boman

引用次数: 46

DeltaSyn: An efficient logic difference optimizer for ECO synthesis DeltaSyn:一个高效的ECO合成逻辑差分优化器

2009 IEEE/ACM International Conference on Computer-Aided Design - Digest of Technical Papers Pub Date : 2009-11-02 DOI: 10.1145/1687399.1687546

Smita Krishnaswamy, Haoxing Ren, Nilesh A. Modi, R. Puri

{"title":"DeltaSyn: An efficient logic difference optimizer for ECO synthesis","authors":"Smita Krishnaswamy, Haoxing Ren, Nilesh A. Modi, R. Puri","doi":"10.1145/1687399.1687546","DOIUrl":"https://doi.org/10.1145/1687399.1687546","url":null,"abstract":"During the IC design process, functional specifications are often modified late in the design cycle, after placement and routing are completed. However, designers are left either to manually process such modifications by hand or to restart the design process from scratch - a very costly option. In order to address this issue, we present DeltaSyn, a method for generating a highly optimized logic difference between a modified high-level specification and an implemented design. DeltaSyn has the ability to locate boundaries in implemented logic within which changes can be confined. Delta-Syn demarcates the boundary in two phases. The first phase employs fast functional and structural analysis techniques to identify equivalent signals forming the input-side boundary of the changes. The second phase locates the output-side boundary of the changes through a novel dynamic algorithm that detects matching logic downstream from the changes required by the ECO. Experiments on industrial designs show that together these techniques successfully implement ECOs while preserving an average of 97% of the existing logic. Unlike previous approaches, the use of bit-parallel logic simulation and fast SAT solvers enables high performance and scalability. DeltaSyn can process and verify a typical ECO for a design of around 10K gates in about 200 seconds or less.","PeriodicalId":256358,"journal":{"name":"2009 IEEE/ACM International Conference on Computer-Aided Design - Digest of Technical Papers","volume":"28 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2009-11-02","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127426178","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 48

Obstacle-avoiding rectilinear Steiner tree construction based on Steiner point selection 基于斯坦纳点选择的避障直线斯坦纳树构造

2009 IEEE/ACM International Conference on Computer-Aided Design - Digest of Technical Papers Pub Date : 2009-11-02 DOI: 10.1145/1687399.1687406

Chih-Hung Liu, Shih-Yi Yuan, S. Kuo, Jung-Hung Weng

引用次数: 19

Consistency-based characterization for IC Trojan detection 基于一致性的IC木马检测表征

2009 IEEE/ACM International Conference on Computer-Aided Design - Digest of Technical Papers Pub Date : 2009-11-02 DOI: 10.1145/1687399.1687426

Y. Alkabani, F. Koushanfar

引用次数: 103

From 2D to 3D NoCs: A case study on worst-case communication performance 从2D到3D noc:最坏情况下通信性能的案例研究

2009 IEEE/ACM International Conference on Computer-Aided Design - Digest of Technical Papers Pub Date : 2009-11-02 DOI: 10.1145/1687399.1687504

Yue Qian, Zhonghai Lu, Wenhua Dou

引用次数: 31