Proceedings of the 25th edition on Great Lakes Symposium on VLSI最新文献_第4页

Online and Operand-Aware Detection of Failures Utilizing False Alarm Vectors 基于虚警矢量的在线和操作数感知故障检测

Proceedings of the 25th edition on Great Lakes Symposium on VLSI Pub Date : 2015-05-20 DOI: 10.1145/2742060.2742097

A. Yazdanbakhsh, David J. Palframan, A. Davoodi, N. Kim, Mikko H. Lipasti

引用次数: 0

Session details: Reliability, Resiliency, Robustness I 会话细节:可靠性，弹性，鲁棒性

Proceedings of the 25th edition on Great Lakes Symposium on VLSI Pub Date : 2015-05-20 DOI: 10.1145/3254006

Jie Han

引用次数: 0

Characterization of SWCNT Bundle Based VLSI Interconnect with Self-heating Induced Scatterings 基于自热诱导散射的SWCNT束VLSI互连特性研究

Proceedings of the 25th edition on Great Lakes Symposium on VLSI Pub Date : 2015-05-20 DOI: 10.1145/2742060.2742074

K. M. Mohsin, A. Srivastava

引用次数: 4

Electromigration-aware Clock Tree Synthesis for TSV-based 3D-ICs 基于tsv的3d集成电路的电迁移感知时钟树合成

Proceedings of the 25th edition on Great Lakes Symposium on VLSI Pub Date : 2015-05-20 DOI: 10.1145/2742060.2742068

Tiantao Lu, Ankur Srivastava

引用次数: 7

ApproxMA: Approximate Memory Access for Dynamic Precision Scaling 近似内存访问动态精确缩放

Proceedings of the 25th edition on Great Lakes Symposium on VLSI Pub Date : 2015-05-20 DOI: 10.1145/2742060.2743759

Ye Tian, Qian Zhang, Ting Wang, F. Yuan, Q. Xu

引用次数: 44

Analyzing the Dark Silicon Phenomenon in a Many-Core Chip Multi-Processor under Deeply-Scaled Process Technologies 深加工技术下多核芯片多处理器中的暗硅现象分析

Proceedings of the 25th edition on Great Lakes Symposium on VLSI Pub Date : 2015-05-20 DOI: 10.1145/2742060.2742096

A. Shafaei, Yanzhi Wang, Srikanth Ramadurgam, Yuankun Xue, P. Bogdan, Massoud Pedram

{"title":"Analyzing the Dark Silicon Phenomenon in a Many-Core Chip Multi-Processor under Deeply-Scaled Process Technologies","authors":"A. Shafaei, Yanzhi Wang, Srikanth Ramadurgam, Yuankun Xue, P. Bogdan, Massoud Pedram","doi":"10.1145/2742060.2742096","DOIUrl":"https://doi.org/10.1145/2742060.2742096","url":null,"abstract":"The impact of dark silicon phenomenon on multicore processors under deeply-scaled FinFET technologies is investigated in this paper. To do this accurately, a cross-layer framework, spanning device, circuit, and architecture levels is initially introduced. Using this framework, leakage and dynamic power consumptions as well as frequency levels of in-order and out-of-order (OoO) processor cores, and on-chip cache memories and routers in a network-on-chip-based chip multiprocessor system synthesized in 7nm FinFET technology and operating in both super- and near-threshold voltage regimes are presented. Subsequently, total power consumptions of multicore chips manufactured with (i) OoO and (ii) in-order processor cores are reported and compared. According to our results, for a 64-core chip and 15W thermal design power budget, 64% and 39% dark silicon are observed in OoO and in-order multicores, respectively, under super-threshold regime. These percentages drop to 19% and 0% for OoO and in-order multicores operating in the near-threshold regime, respectively. Furthermore, the highest energy efficiencies are achieved by operating in the near-threshold regime, which points to the effectiveness of near-threshold computing in mitigating the effect of dark silicon phenomenon under deeply-scaled technologies.","PeriodicalId":255133,"journal":{"name":"Proceedings of the 25th edition on Great Lakes Symposium on VLSI","volume":"30 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2015-05-20","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121297480","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 4

NeuroDSP Accelerator for Face Detection Application NeuroDSP加速器的人脸检测应用

Proceedings of the 25th edition on Great Lakes Symposium on VLSI Pub Date : 2015-05-20 DOI: 10.1145/2742060.2743769

M. Paindavoine, O. Boisard, Alexandre Carbon, Jean-Marc Philippe, O. Brousse

引用次数: 4

TFET-based Operational Transconductance Amplifier Design for CNN Systems 基于tfet的CNN系统运算跨导放大器设计

Proceedings of the 25th edition on Great Lakes Symposium on VLSI Pub Date : 2015-05-20 DOI: 10.1145/2742060.2742089

Qiuwen Lou, Indranil Palit, A. Horváth, X. Hu, M. Niemier, J. Nahas

{"title":"TFET-based Operational Transconductance Amplifier Design for CNN Systems","authors":"Qiuwen Lou, Indranil Palit, A. Horváth, X. Hu, M. Niemier, J. Nahas","doi":"10.1145/2742060.2742089","DOIUrl":"https://doi.org/10.1145/2742060.2742089","url":null,"abstract":"A Cellular Neural Network (CNN) is a powerful processor that can significantly improve the performance of spatio-temporal applications such as pattern recognition, image processing, motion detection, when compared to the more traditional von Neumann architecture. In this paper, we show how tunneling field effect transistors (TFETs) can be utilized to enhance the performance of CNNs. Specifically, power consumption of TFET-based CNNs can be significantly lower when compared to MOSFET-based CNNs due to improved voltage controlled current sources (VCCSs) - an important component in CNN systems. We demonstrate that CNNs can benefit from low power conventional linear VCCSs implemented via TFETs. We also show that TFETs can be useful to realize non-linear VCCSs, which are either not possible or exhibit degraded performance when implemented via CMOS. Such non-linear VCCSs help to improve the performance of certain CNN operations (e.g., global maximum/minimum). We provide two case studies - image contrast enhancement and maximum row selection - that illustrate the benefits of non-linear VCCSs (e.g., reduced computation time, energy dissipation, etc.) when compared to CMOS-based approaches.","PeriodicalId":255133,"journal":{"name":"Proceedings of the 25th edition on Great Lakes Symposium on VLSI","volume":"157 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2015-05-20","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131300742","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 8

Multi Replica Bitline Delay Technique for Variation Tolerant Timing of SRAM Sense Amplifiers SRAM感测放大器容差时序的多副本位线延迟技术

Proceedings of the 25th edition on Great Lakes Symposium on VLSI Pub Date : 2015-05-20 DOI: 10.1145/2742060.2742065

Samira Ataei, J. Stine

引用次数: 6

A Dynamically Reconfigurable RF NoC for Many-Core 一种多核动态可重构射频NoC

Proceedings of the 25th edition on Great Lakes Symposium on VLSI Pub Date : 2015-05-20 DOI: 10.1145/2742060.2742082

Alexandre Briere, J. Denoulet, A. Pinna, B. Granado, F. Pêcheux, Eren Unlu, Y. Louët, C. Moy

{"title":"A Dynamically Reconfigurable RF NoC for Many-Core","authors":"Alexandre Briere, J. Denoulet, A. Pinna, B. Granado, F. Pêcheux, Eren Unlu, Y. Louët, C. Moy","doi":"10.1145/2742060.2742082","DOIUrl":"https://doi.org/10.1145/2742060.2742082","url":null,"abstract":"With the growing number of cores on chips, conventional electrical interconnects reach scalability limits, leading the way for alternatives like Radio Frequency (RF), optical and 3D. Due to the variability of applications, communication needs change over time and across regions of the chip. To address these issues, a dynamically reconfigurable Network on Chip (NoC) is proposed. It uses RF and Orthogonal Frequency Division Multiple Access (OFDMA) to create communication channels whose allocation allows dynamic reconfiguration. We describe the NoC architecture and the distributed mechanism of dynamic allocation. We study the feasibility of the NoC based on state of the art components and analyze its performances. Static analysis shows that, for point to point communications, its latency is comparable with a 256-node electrical mesh and becomes lower for wider networks. A major feature of this architecture is its broadcast capacity. The RF~NoC becomes faster with 32 nodes, achieving a x3 speedup with 1024. Under realistic traffic models, its dynamic reconfigurability provides up to x6 lower latency while ensuring fairness.","PeriodicalId":255133,"journal":{"name":"Proceedings of the 25th edition on Great Lakes Symposium on VLSI","volume":"2 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2015-05-20","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116129851","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 12