Proceedings of the 25th edition on Great Lakes Symposium on VLSI最新文献

Session details: Reliability, Resiliency, Robustness II 会话细节:可靠性，弹性，稳健性II

Proceedings of the 25th edition on Great Lakes Symposium on VLSI Pub Date : 2015-05-20 DOI: 10.1145/3254010

S. Cotofana

引用次数: 0

Design and Characterization of Analog-to-Digital Converters using Graphene P-N Junctions 石墨烯P-N结模数转换器的设计与表征

Proceedings of the 25th edition on Great Lakes Symposium on VLSI Pub Date : 2015-05-20 DOI: 10.1145/2742060.2742099

R. G. Rizzo, S. Miryala, A. Calimera, E. Macii, M. Poncino

{"title":"Design and Characterization of Analog-to-Digital Converters using Graphene P-N Junctions","authors":"R. G. Rizzo, S. Miryala, A. Calimera, E. Macii, M. Poncino","doi":"10.1145/2742060.2742099","DOIUrl":"https://doi.org/10.1145/2742060.2742099","url":null,"abstract":"Electrostatically controlled graphene p-n junctions are devices built on single-layer graphene sheets whose in-to-out resistance can be dynamically tuned through external voltage potentials. While several recent works mainly focused on the possibility of using those devices as a new logic primitive for digital circuits, in this paper we address a complementary problem, that is, how to efficiently implement Analog-to-Digital Converters (ADCs) that can be integrated in future all-graphene flexible ICs. The contribution of this work is threefold: (i) introduce a new ADC architecture that perfectly matches with the main characteristics of graphene p-n junctions; (ii) give a first, yet detailed parametric characterization of the proposed ADC architecture as to validate its functionality and quantify its figures of merit; (iii) provide a fully automated design flow that, given as input the design specs, i.e., input voltage range, voltage resolution and sampling rate, returns an optimally sized ADC circuitry. Few case studies also demonstrate p-n junction based graphene ADCs have characteristics in line with those offered by todays' CMOS ones.","PeriodicalId":255133,"journal":{"name":"Proceedings of the 25th edition on Great Lakes Symposium on VLSI","volume":"14 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2015-05-20","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125849328","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 2

Yield-aware Performance-Cost Characterization for Multi-Core SIMT 多核SIMT的产率感知性能成本表征

Proceedings of the 25th edition on Great Lakes Symposium on VLSI Pub Date : 2015-05-20 DOI: 10.1145/2742060.2742112

S. H. Mozafari, B. Meyer, K. Skadron

引用次数: 7

Session details: Emerging Technologies 会议详情:新兴技术

Proceedings of the 25th edition on Great Lakes Symposium on VLSI Pub Date : 2015-05-20 DOI: 10.1145/3254014

Yiran Chen

引用次数: 0

Graphene Neural Sensors for Next Generation In Vivo Imaging and Optogenetics 下一代体内成像和光遗传学石墨烯神经传感器

Proceedings of the 25th edition on Great Lakes Symposium on VLSI Pub Date : 2015-05-20 DOI: 10.1145/2742060.2745702

Z. Ma

引用次数: 0

Approximate Multiplier Architectures Through Partial Product Perforation: Power-Area Tradeoffs Analysis 通过部分乘积穿孔的近似乘法器结构:功率面积权衡分析

Proceedings of the 25th edition on Great Lakes Symposium on VLSI Pub Date : 2015-05-20 DOI: 10.1145/2742060.2742109

Georgios Zervakis, Kostas Tsoumanis, S. Xydis, N. Axelos, K. Pekmestzi

{"title":"Approximate Multiplier Architectures Through Partial Product Perforation: Power-Area Tradeoffs Analysis","authors":"Georgios Zervakis, Kostas Tsoumanis, S. Xydis, N. Axelos, K. Pekmestzi","doi":"10.1145/2742060.2742109","DOIUrl":"https://doi.org/10.1145/2742060.2742109","url":null,"abstract":"Approximate computing has received significant attention as a promising strategy to decrease power consumption of inherently error-tolerant applications. Hardware approximation mainly targets arithmetic units, e.g. adders and multipliers. In this paper, we design new approximate hardware multipliers and propose the Partial Product Perforation technique, which omits a number of consecutive partial products by perforating their generation. Through extensive experimental evaluation, we apply the partial product perforation method on different multiplier architectures and expose the optimal configurations for different error values. We show that the partial product perforation delivers reductions of up to 50% in power consumption, 45% in area and 35% in critical delay. Also, the product perforation method is compared with state-of-the-art works on approximate computing that consider the Voltage Over-Scaling (VOS) and logic approximation (i.e. design of approximate compressors) techniques, outperforming them in terms of power dissipation by up to 17% and 20% on average respectively. Finally, with respect to the aforementioned gains, the error value delivered by the proposed product perforation method is smaller by 70% and 99% than the VOS and logic approximation methods respectively.","PeriodicalId":255133,"journal":{"name":"Proceedings of the 25th edition on Great Lakes Symposium on VLSI","volume":"70 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2015-05-20","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123667250","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 17

An Effective TSV Self-Repair Scheme for 3D-Stacked ICs 一种有效的3d堆叠集成电路TSV自修复方案

Proceedings of the 25th edition on Great Lakes Symposium on VLSI Pub Date : 2015-05-20 DOI: 10.1145/2742060.2742071

Songwei Pei, Jingdong Zhang, Yu Jin, Song Jin, Jun Liu, Weizhi Xu

引用次数: 0

Revisiting Dynamic Thermal Management Exploiting Inverse Thermal Dependence 利用逆热依赖重温动态热管理

Proceedings of the 25th edition on Great Lakes Symposium on VLSI Pub Date : 2015-05-20 DOI: 10.1145/2742060.2742086

Katayoun Neshatpour, H. Homayoun, A. Djahromi, W. Burleson

{"title":"Revisiting Dynamic Thermal Management Exploiting Inverse Thermal Dependence","authors":"Katayoun Neshatpour, H. Homayoun, A. Djahromi, W. Burleson","doi":"10.1145/2742060.2742086","DOIUrl":"https://doi.org/10.1145/2742060.2742086","url":null,"abstract":"As CMOS technology scales down towards nanometer regime and the supply voltage approaches the threshold voltage, increase in operating temperature results in increased circuit current, which in turn reduces circuit propagation delay. This paper exploits this new phenomenon, known as inverse thermal dependence (ITD) for power, performance, and temperature optimization in processor architecture. ITD changes the maximum achievable operating frequency of the processor at high temperatures. Dynamic thermal management techniques such as activity migration, dynamic voltage frequency scaling, and throttling are revisited in this paper, with a focus on the effect of ITD. Results are obtained using the predictive technology models of 7nm, 10nm 14nm and 20nm technology nodes and with extensive architectural and circuit simulations. The results show that based on the design goals, various design corners should be re-investigated for power, performance and energy-efficiency optimization. Architectural simulations for a multi-core processor and across standard benchmarks show that utilizing ITD-aware schemes for thermal management improves the performance of the processor in terms of speed and energy-delay-product by 8.55% and 4.4%, respectively.","PeriodicalId":255133,"journal":{"name":"Proceedings of the 25th edition on Great Lakes Symposium on VLSI","volume":"30 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2015-05-20","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132388251","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 1

Session details: Keynote IV 会议详情:主题演讲四

Proceedings of the 25th edition on Great Lakes Symposium on VLSI Pub Date : 2015-05-20 DOI: 10.1145/3254021

M. Margala

引用次数: 0

Dynamic Bitstream Length Scaling Energy Effective Stochastic LDPC Decoding 动态比特流长度缩放能量有效随机LDPC解码

Proceedings of the 25th edition on Great Lakes Symposium on VLSI Pub Date : 2015-05-20 DOI: 10.1145/2742060.2742117

T. Marconi, S. Cotofana

{"title":"Dynamic Bitstream Length Scaling Energy Effective Stochastic LDPC Decoding","authors":"T. Marconi, S. Cotofana","doi":"10.1145/2742060.2742117","DOIUrl":"https://doi.org/10.1145/2742060.2742117","url":null,"abstract":"Stochastic Computing (SC) is an attractive solution for implementing Low Density Parity Codes (LDPC) decoders due to its fault tolerance capability and low hardware requirements. However, in practical implementations, SC efficiency is limited by the Stochastic Bitstream (SB) length and by the computation inaccuracies due to non-unique SB representations. In this paper, rather than statically fixing the SB length at run-time, we propose a Dynamic Bitstream Length Scaling (DBLS) technique, which adjusts on-the-fly the SB length such that Quality of Service requirements for energy efficient LDPC decoding are fulfilled. In this way, depending on the communication channel condition, different SB lengths are adaptively utilized such that the best decoding performance vs energy consumption tradeoff is achieved. To evaluate the DBLS practical implications we selected an (1296,648) LDPC with dv=3 and dc=6 and implemented our approach and the best state-of-the-art stochastic LDPC decoder with 64-bit edge memory on a Virtex-7 FPGA. Experimental results indicate that our proposal requires 9% more FFs and 3% more LUTs while diminishing the energy consumption by 31-80% and providing 1.5-5.1x higher throughput.","PeriodicalId":255133,"journal":{"name":"Proceedings of the 25th edition on Great Lakes Symposium on VLSI","volume":"44 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2015-05-20","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130766258","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 1