Proceedings of the 25th edition on Great Lakes Symposium on VLSI最新文献_第10页

Automation of Biological Model Learning, Design and Analysis 生物模型学习、设计与分析的自动化

Proceedings of the 25th edition on Great Lakes Symposium on VLSI Pub Date : 2015-05-20 DOI: 10.1145/2742060.2743765

Nataša Miškov-Živanov

引用次数: 8

Reinforcement Learning for Thermal-aware Many-core Task Allocation 热感知多核任务分配的强化学习

Proceedings of the 25th edition on Great Lakes Symposium on VLSI Pub Date : 2015-05-20 DOI: 10.1145/2742060.2742078

Shiting Lu, R. Tessier, W. Burleson

引用次数: 27

Session details: CAD and Circuits II 会议细节:CAD和电路II

Proceedings of the 25th edition on Great Lakes Symposium on VLSI Pub Date : 2015-05-20 DOI: 10.1145/3254024

M. Velev

引用次数: 0

Session details: Special Session: Advances in Neuromorphic Architectures and Future Applications 特别会议:神经形态架构和未来应用的进展

Proceedings of the 25th edition on Great Lakes Symposium on VLSI Pub Date : 2015-05-20 DOI: 10.1145/3254012

C. Chavet

引用次数: 0

A High-Speed Robust NVM-TCAM Design Using Body Bias Feedback 基于车身偏置反馈的高速稳健NVM-TCAM设计

Proceedings of the 25th edition on Great Lakes Symposium on VLSI Pub Date : 2015-05-20 DOI: 10.1145/2742060.2742077

Bonan Yan, Zheng Li, Yaojun Zhang, Jianlei Yang, Hai Helen Li, Weisheng Zhao, P. Chia

{"title":"A High-Speed Robust NVM-TCAM Design Using Body Bias Feedback","authors":"Bonan Yan, Zheng Li, Yaojun Zhang, Jianlei Yang, Hai Helen Li, Weisheng Zhao, P. Chia","doi":"10.1145/2742060.2742077","DOIUrl":"https://doi.org/10.1145/2742060.2742077","url":null,"abstract":"As manufacture process scales down rapidly, the design of ternary content-addressable memory (TCAM) requiring high storage density, fast access speed and low power consumption becomes very challenging. In recent years, many novel TCAM designs have been inspired by the research on emerging nonvolatile memory technologies, such as magnetic tunneling junction (MTJ), phase change memory (PCM), and memristor. These designs store a data as the resistive variable of a nonvolatile device, which usually results in limited sensing margin and therefore constrains the searching speed of TCAM architecture severely. To further enhance the performance and robustness of TCAMs, we proposed two novel cell designs that utilize MTJs as data storage units - the symmetrical dual-N structure and the asymmetrical P-N scheme. In both designs, a body bias feedback circuit is integrated to enlarge the sensing margins. Compared with an existing MTJ-based TCAM structure, the tolerance in gate voltage variation of the symmetrical dua-N (asymmetrical P-N) scheme can significantly improve 59.5% (21.2%). The latency and the dynamic energy consumption in one searching operation at the word length of 256 bits are merely 590.35ps (97.89ps) and 65.05fJ/bit (36.85fJ/bit), not even mentioning that the use of nonvolatile MTJ devices avoids unnecessary leakage power consumption.","PeriodicalId":255133,"journal":{"name":"Proceedings of the 25th edition on Great Lakes Symposium on VLSI","volume":"765 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2015-05-20","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"117015219","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 16

Session details: Power and Temperature-Aware Design 会议细节:电源和温度感知设计

Proceedings of the 25th edition on Great Lakes Symposium on VLSI Pub Date : 2015-05-20 DOI: 10.1145/3254025

Bei Yu

引用次数: 0

Playing with Fire: Transactional Memory Revisited for Error-Resilient and Energy-Efficient MPSoC Execution 玩火:重新访问事务性内存以实现容错和节能的MPSoC执行

Proceedings of the 25th edition on Great Lakes Symposium on VLSI Pub Date : 2015-05-20 DOI: 10.1145/2742060.2742090

Dimitra Papagiannopoulou, A. Marongiu, T. Moreshet, L. Benini, M. Herlihy, R. I. Bahar

{"title":"Playing with Fire: Transactional Memory Revisited for Error-Resilient and Energy-Efficient MPSoC Execution","authors":"Dimitra Papagiannopoulou, A. Marongiu, T. Moreshet, L. Benini, M. Herlihy, R. I. Bahar","doi":"10.1145/2742060.2742090","DOIUrl":"https://doi.org/10.1145/2742060.2742090","url":null,"abstract":"As silicon integration technology pushes toward atomic dimensions, errors due to static and dynamic variability are an increasing concern. To avoid such errors, designers often turn to \"guardband\" restrictions on the operating frequency and voltage. If guardbands are too conservative, they limit performance and waste energy, but less conservative guardbands risk moving the system closer to its Critical Operating Point (COP), a frequency-voltage pair that, if surpassed, causes massive instruction failures. In this paper, we propose a novel scheme that allows to dynamically adjust to an evolving COP and operate at highly reduced margins, while guaranteeing forward progress. Specifically, our scheme dynamically monitors the platform and adaptively adjusts to the COP among multiple cores, using lightweight checkpointing and roll-back mechanisms adopted from Hardware Transactional Memory (HTM) for error recovery. Experiments demonstrate that our technique is particularly effective in saving energy while also offering safe execution guarantees. To the best of our knowledge, this work is the first to describe a full-fledged HTM implementation for error-resilient and energy-efficient MPSoC execution.","PeriodicalId":255133,"journal":{"name":"Proceedings of the 25th edition on Great Lakes Symposium on VLSI","volume":"168 9 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2015-05-20","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125991301","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 6

Session details: Special Session: Neuromorphic Computing based on Resistive Devices 专题会议:基于电阻器件的神经形态计算

Proceedings of the 25th edition on Great Lakes Symposium on VLSI Pub Date : 2015-05-20 DOI: 10.1145/3254011

Nataša Miškov-Živanov

引用次数: 0

A Novel True Random Number Generator Design Leveraging Emerging Memristor Technology 一种利用新兴忆阻器技术的真随机数发生器设计

Proceedings of the 25th edition on Great Lakes Symposium on VLSI Pub Date : 2015-05-20 DOI: 10.1145/2742060.2742088

Yandan Wang, W. Wen, Hai Helen Li, Miao Hu

{"title":"A Novel True Random Number Generator Design Leveraging Emerging Memristor Technology","authors":"Yandan Wang, W. Wen, Hai Helen Li, Miao Hu","doi":"10.1145/2742060.2742088","DOIUrl":"https://doi.org/10.1145/2742060.2742088","url":null,"abstract":"Memristor, the fourth basic circuit element, demonstrates obvious stochastic behaviors in both the static resistance states and the dynamic switching. In this work, a novel memristor-based true random number generator (MTRNG) is presented which leverages the stochastic property when switching a device between its binary states. Compared to conventional random number generators that require amplifiers or comparators with high complexity, the use of memristors significantly reduces the design cost: a basic MTRNG consists of only one memristor, six transistors, and one D Flip-flop. To maximize the entropy of the random bit generation, we further enhanced the design to a 2-branch scheme which can provide a uniform bit distribution. Our simulation results show that the proposed MTRNGs offer high operating speed and low power consumption: the reading clocks of the basic 1-branch and the enhanced 2-branch schemes can reach at 1.05GHz and 0.96GHz with power assumptions of 31.1\"W and 80.3\"W, respectively. Moreover, the zero-versus-one distributions and sampling rates of MTRNGs can be flexibly reconfigured by modulating the width and amplitude of the programming pulse applied on a memristor and therefore adjusting its switching probability between ON and OFF states.","PeriodicalId":255133,"journal":{"name":"Proceedings of the 25th edition on Great Lakes Symposium on VLSI","volume":"45 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2015-05-20","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121909387","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 41