Proceedings of the 25th edition on Great Lakes Symposium on VLSI最新文献_第9页

A Novel Framework for Temperature Dependence Aware Clock Skew Scheduling 一种温度依赖性感知时钟偏差调度的新框架

Proceedings of the 25th edition on Great Lakes Symposium on VLSI Pub Date : 2015-05-20 DOI: 10.1145/2742060.2742073

M. Kaneko

{"title":"A Novel Framework for Temperature Dependence Aware Clock Skew Scheduling","authors":"M. Kaneko","doi":"10.1145/2742060.2742073","DOIUrl":"https://doi.org/10.1145/2742060.2742073","url":null,"abstract":"Temperature is one of the major sources of delay variations which may cause timing violations. In this paper, an approach to temperature aware clock skew scheduling for a general class of sequential circuits is proposed. At first, an alternative interpretation of the affine type (linear model) of temperature dependency is shown, which is not merely a \"linearized\" model applicable to a limited temperature range, but it can cover a class of nonlinear temperature dependency, and hence its applicability is not limited in temperature range. After that, a graph-theoretic skew scheduling considering the lower and the upper temperature bounds, which can work in a polynomial time complexity with respect to the circuit size, is derived. This framework can be applicable to the variants of temperature aware optimizations, such as maximizing upper temperature bound, maximizing clock frequency under a given temperature range, etc. Experiments using ISCAS'89 benchmark circuits show us that our approach achieves maximum 70% improvement in the upper temperature range (in a linear temperature scale) compared with a conventional skew scheduling which maximizes the minimum timing slack.","PeriodicalId":255133,"journal":{"name":"Proceedings of the 25th edition on Great Lakes Symposium on VLSI","volume":"9 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2015-05-20","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114072768","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 1

Session details: CAD and Circuits I 会议细节:CAD和电路1

Proceedings of the 25th edition on Great Lakes Symposium on VLSI Pub Date : 2015-05-20 DOI: 10.1145/3254020

F. Lombardi

引用次数: 0

Efficient Reliability Analysis of Processor Datapath using Atomistic BTI Variability Models 基于原子BTI可变性模型的处理器数据路径高效可靠性分析

Proceedings of the 25th edition on Great Lakes Symposium on VLSI Pub Date : 2015-05-20 DOI: 10.1145/2742060.2742079

Dimitrios Stamoulis, D. Rodopoulos, B. Meyer, D. Soudris, F. Catthoor, Z. Zilic

引用次数: 11

Adaptive Bandwidth Management for Performance-Temperature Trade-offs in Heterogeneous HMC+DDRx Memory 异构HMC+DDRx内存中性能-温度权衡的自适应带宽管理

Proceedings of the 25th edition on Great Lakes Symposium on VLSI Pub Date : 2015-05-20 DOI: 10.1145/2742060.2742070

Mohammad Hossein Hajkazemi, Michael Chorney, Reyhaneh Jabbarvand Behrouz, Mohammad Khavari Tavana, H. Homayoun

{"title":"Adaptive Bandwidth Management for Performance-Temperature Trade-offs in Heterogeneous HMC+DDRx Memory","authors":"Mohammad Hossein Hajkazemi, Michael Chorney, Reyhaneh Jabbarvand Behrouz, Mohammad Khavari Tavana, H. Homayoun","doi":"10.1145/2742060.2742070","DOIUrl":"https://doi.org/10.1145/2742060.2742070","url":null,"abstract":"High fabrication cost per bit and thermal issues are the main reasons that prevent architects from using 3D-DRAM alone as the main memory. In this paper we address this issue by proposing a heterogeneous memory system that combines a DDRx DRAM with an emerging 3D hybrid memory cube (HMC) technology. Bandwidth and temperature management are the challenging issues for such heterogeneous memory architecture. To address these challenges, first we introduce a memory page allocation policy for the heterogeneous memory system to maximize performance. Then, using the proposed memory page allocation policy, we propose a temperature-aware algorithm that adaptively distributes the requested bandwidth between HMC and DDRx DRAM to reduce the thermal hotspot while maintaining high performance. The results show that the proposed memory page allocation policy can utilize the memory bandwidth close to 99% of the ideal bandwidth utilization. Moreover our temperate-aware bandwidth adaptation reduces the average steady-state temperature of the HMC hotspot across various workloads by 4.5oK while incurring 2.5% performance overhead.","PeriodicalId":255133,"journal":{"name":"Proceedings of the 25th edition on Great Lakes Symposium on VLSI","volume":"73 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2015-05-20","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128980105","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 8

MSCS: Multi-hop Segmented Circuit Switching 多跳分段电路交换

Proceedings of the 25th edition on Great Lakes Symposium on VLSI Pub Date : 2015-05-20 DOI: 10.1145/2742060.2742087

Donald Kline, Kai Wang, R. Melhem, A. Jones

{"title":"MSCS: Multi-hop Segmented Circuit Switching","authors":"Donald Kline, Kai Wang, R. Melhem, A. Jones","doi":"10.1145/2742060.2742087","DOIUrl":"https://doi.org/10.1145/2742060.2742087","url":null,"abstract":"NoCs (networks-on-chip) are commonly proposed as scalable on-chip interconnects for current and future CMPs (chip multi-processors) and many-core systems. While scalable, the lack of global control can create routing inefficiencies detrimental to the overall network latency. Recently, NoCs have been proposed that allow flits to traverse multiple network switches in a single cycle. This requires a more global view of control to allow routers along the path of a packet to configure their switches collectively. In this paper, we propose a reservation based circuit-switching design, MSCS, which provides simplified global control and multi-hop traversal while reducing latency. MSCS performs network control once per network dimension for the lifetime of a packet, while the leading methods require multiple arbitration steps depending on contention in the network. Furthermore, MSCS can perform control for a packet prior to the availability of resources through reservations, while previous schemes only perform control on-demand. Overall, MSCS can reduce the buffer size by 50% over the leading multi-hop scheme while maintaining a nominal latency improvement (1.4%). With the same buffer resources per port, MSCS achieves a 12.7% latency improvement.","PeriodicalId":255133,"journal":{"name":"Proceedings of the 25th edition on Great Lakes Symposium on VLSI","volume":"17 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2015-05-20","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131983016","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 5

Session details: Best Paper Session 会议细节:最佳论文会议

Proceedings of the 25th edition on Great Lakes Symposium on VLSI Pub Date : 2015-05-20 DOI: 10.1145/3254015

A. Coskun

引用次数: 0

Session details: Energy Efficient Systems 会议详情:能源效率系统

Proceedings of the 25th edition on Great Lakes Symposium on VLSI Pub Date : 2015-05-20 DOI: 10.1145/3254008

B. Taskin

引用次数: 0

Standard Cell Layout Regularity and Pin Access Optimization Considering Middle-of-Line 考虑中线的标准单元布局规则和引脚接入优化

Proceedings of the 25th edition on Great Lakes Symposium on VLSI Pub Date : 2015-05-20 DOI: 10.1145/2742060.2742084

Wei Ye, Bei Yu, D. Pan, Y. Ban, L. Liebmann

引用次数: 34

Digital Microfluidic Biochips: Towards Functional Diversity, More than Moore, and Cyberphysical Integration 数字微流控生物芯片:迈向功能多样性，超过摩尔，和网络物理集成

Proceedings of the 25th edition on Great Lakes Symposium on VLSI Pub Date : 2015-05-20 DOI: 10.1145/2742060.2745701

K. Chakrabarty

{"title":"Digital Microfluidic Biochips: Towards Functional Diversity, More than Moore, and Cyberphysical Integration","authors":"K. Chakrabarty","doi":"10.1145/2742060.2745701","DOIUrl":"https://doi.org/10.1145/2742060.2745701","url":null,"abstract":"Advances in droplet-based \"digital\" microfluidics have led to the emergence of biochip devices for automating laboratory procedures in biochemistry and molecular biology. These devices enable the precise control of nanoliter-volume droplets of biochemical samples and reagents. Therefore, integrated circuit (IC) technology can be used to transport and transport \"chemical payload\" in the form of micro/nanofluidic droplets. As a result, non-traditional biomedical applications and markets (e.g., high-throughout DNA sequencing, portable and point-of-care clinical diagnostics, protein crystallization for drug discovery), and fundamentally new uses are opening up for ICs and systems. However, continued growth depends on advances in chip integration and design-automation tools. Design automation is needed to ensure that biochips are as versatile as the macro-labs that they are intended to replace, and researchers can thereby envision an automated design flow for biochips, in the same way as design automation revolutionized IC design in the 80s and 90s. This talk will first provide an overview of market drivers such as immunoassays, DNA sequencing, clinical chemistry, etc., and electrowetting-based digital microfludic biochips. The audience will next learn about design automation, design-for-testability, and reconfiguration aspects of digital microfluidic biochips. Synthesis tools will be described to map assay protocols from the lab bench to a droplet-based microfluidic platform and generate an optimized schedule of bioassay operations, the binding of assay operations to functional units, and the layout and droplet-flow paths for the biochip. The role of the digital microfluidic platform as a \"programmable and reconfigurable processor\" for biochemical applications will be highlighted. Finally, the speaker will demonstrate dynamic adaptation of bioassays through cyberphysical system integration and sensor-driven on-chip error recovery.","PeriodicalId":255133,"journal":{"name":"Proceedings of the 25th edition on Great Lakes Symposium on VLSI","volume":"15 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2015-05-20","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131307705","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

Reconfigurable Silicon-Photonic Network with Improved Channel Sharing for Multicore Architectures 基于改进通道共享的多核结构可重构硅光子网络

Proceedings of the 25th edition on Great Lakes Symposium on VLSI Pub Date : 2015-05-20 DOI: 10.1145/2742060.2742067

S. V. R. Chittamuru, Srinivas Desai, S. Pasricha

引用次数: 18