Electromigration-aware Clock Tree Synthesis for TSV-based 3D-ICs

In 3D-IC technology, electromigration (EM) degradation has become severe due to the high thermal-mechanical stress induced by the Through-Silicon-Vias (TSVs). However, little has been done on designing an EM-robust clock tree for 3D-ICs. In this paper, we propose a systematic EM-aware clock tree synthesis design flow, to enhance the 3D clock tree's EM reliability, with little interference to clock tree's performance metrics such as total wire length and clock skew. We develop a simple TSV's EM objective function based on multi-physics of the mass transportation equation, and validate it against the finite element method (FEM) simulation. Then we use this objective function to formulate a heuristic, based on integer linear programming (ILP), which places the clock TSVs such that the clock tree's EM reliability is maximized. Results show that the our heuristic is able to increase 3D clock's EM lifetime by more than 3.63x with little wire length overhead, while maintaining zero clock skew.