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2011 18th IEEE International Conference on Electronics, Circuits, and Systems最新文献

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Design of ultra-wide-load, high-efficient DC-DC buck converters 超宽负载、高效DC-DC降压变换器的设计
2011 18th IEEE International Conference on Electronics, Circuits, and Systems Pub Date : 2011-12-01 DOI: 10.1109/ICECS.2011.6122272
Chinder Wey, Chan-I Chiu, K. Chang, Chung-Hsien Hsu, G. Sung
{"title":"Design of ultra-wide-load, high-efficient DC-DC buck converters","authors":"Chinder Wey, Chan-I Chiu, K. Chang, Chung-Hsien Hsu, G. Sung","doi":"10.1109/ICECS.2011.6122272","DOIUrl":"https://doi.org/10.1109/ICECS.2011.6122272","url":null,"abstract":"The paper presents the design of a current-mode control DC-DC buck converter with pulse-width modulation (PWM) mode. The converter achieves a current load ranged from 50 mA to 500 mA over 90% efficiency, and the maximum power efficiency is 95.6%, where the circuit was simulated with the TSMC 0.35 um CMOS process. In order to achieve ultra-wide-load high efficiency, this paper implements with two PMOS transistors as switches. Results show that the converter achieves above 90% efficiency at the range from 30 mA to 1200 mA with a maximum efficiency of 96.36%. Results show that, with the additional switch transistor, the current load range is expanded more than double. With two PMOS transistors, the proposed converter can also achieve 3 different load ranges so that it can be programmed for the applications which are operated at those three different load ranges.","PeriodicalId":251525,"journal":{"name":"2011 18th IEEE International Conference on Electronics, Circuits, and Systems","volume":"04 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2011-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128999233","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 4
Design and simulation of a switched capacitor ladder filter in a 90nm CMOS technology for WiMAX applications 用于WiMAX应用的90nm CMOS技术开关电容阶梯滤波器的设计与仿真
2011 18th IEEE International Conference on Electronics, Circuits, and Systems Pub Date : 2011-12-01 DOI: 10.1109/ICECS.2011.6122340
Mohamad Reza Nazemi, H. Shamsi, S. Mehregan
{"title":"Design and simulation of a switched capacitor ladder filter in a 90nm CMOS technology for WiMAX applications","authors":"Mohamad Reza Nazemi, H. Shamsi, S. Mehregan","doi":"10.1109/ICECS.2011.6122340","DOIUrl":"https://doi.org/10.1109/ICECS.2011.6122340","url":null,"abstract":"In this paper design and simulation of a 5th order elliptic filter is presented, which its bandwidth is adjustable for WiMAX standard. This filter is realized by a switched capacitor ladder structure. Since the AC analysis of this switched capacitor filter is not possible in HSPICE, so in order to perform the AC analysis the equivalent z-domain model of the filter is also presented. This filter has 156 MHz sampling frequency and its bandwidth is adjustable as follows: 1.25, 2.5, 5, and 10 MHz. This filter has more than 80 dB attenuation at four times of the bandwidth, THD about 64 dB (@Vout =200 mVpp), SFDR more than 67 dB, and power dissipation lower than 35 mW. This filter is designed in a 90nm CMOS technology with a 0.9V supply voltage.","PeriodicalId":251525,"journal":{"name":"2011 18th IEEE International Conference on Electronics, Circuits, and Systems","volume":"44 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2011-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130355946","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 2
Test data compression based on the reuse of parts of the dictionary entries 基于部分字典条目的重用测试数据压缩
2011 18th IEEE International Conference on Electronics, Circuits, and Systems Pub Date : 2011-12-01 DOI: 10.1109/ICECS.2011.6122331
Panagiotis Sismanoglou, D. Nikolos
{"title":"Test data compression based on the reuse of parts of the dictionary entries","authors":"Panagiotis Sismanoglou, D. Nikolos","doi":"10.1109/ICECS.2011.6122331","DOIUrl":"https://doi.org/10.1109/ICECS.2011.6122331","url":null,"abstract":"In this paper we show that the test data compression achieved by a dictionary based method can be improved significantly by suitably reusing parts of the dictionary entries. To this end two new algorithms are proposed, suitable for partial and complete dictionary coding respectively. The efficiency of the proposed techniques is supported with extensive simulation results.","PeriodicalId":251525,"journal":{"name":"2011 18th IEEE International Conference on Electronics, Circuits, and Systems","volume":"17 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2011-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123978591","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 7
Effective throughput 1 Gbps-class millimeter-wave wireless system 有效吞吐量1gbps级毫米波无线系统
2011 18th IEEE International Conference on Electronics, Circuits, and Systems Pub Date : 2011-12-01 DOI: 10.1109/ICECS.2011.6122321
F. Ozawa, T. Taniguchi, Y. Toriyama, J. Kobayashi, Kazuya Kojima
{"title":"Effective throughput 1 Gbps-class millimeter-wave wireless system","authors":"F. Ozawa, T. Taniguchi, Y. Toriyama, J. Kobayashi, Kazuya Kojima","doi":"10.1109/ICECS.2011.6122321","DOIUrl":"https://doi.org/10.1109/ICECS.2011.6122321","url":null,"abstract":"In preparation for achieving the millimeter-wave broadband wireless system aimed at seamless connection with the optical network, we have developed key devices such as baseband signal processing SoC (System-On-Chip) with the built-in high-speed multi-level QAM (Quadrature amplitude modulation) modem (modulator and demodulator), SiGe (silicon germanium) I/Q quadrature modulator and demodulator MMIC (Microwave Monolithic Integrated Circuit), and GaAsHEMT (gallium arsenide high electron mobility transistor) frequency converter MMIC. We have also prototyped the small and broadband 38 GHz band point-to-point wireless system using TDD (Time Division Duplex) mode with dynamic radio resource control. Then, the maximum effective throughput on 64QAM has been 1 Gbps, and this system has reached to the stage of field trial.","PeriodicalId":251525,"journal":{"name":"2011 18th IEEE International Conference on Electronics, Circuits, and Systems","volume":"43 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2011-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123464072","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
256-KB associativity-reconfigurable cache with 7T/14T SRAM for aggressive DVS down to 0.57 V 256-KB关联可重构缓存，7T/14T SRAM，可用于低至0.57 V的主动DVS
2011 18th IEEE International Conference on Electronics, Circuits, and Systems Pub Date : 2011-12-01 DOI: 10.1109/ICECS.2011.6122328
Jinwook Jung, Y. Nakata, S. Okumura, H. Kawaguchi, M. Yoshimoto
{"title":"256-KB associativity-reconfigurable cache with 7T/14T SRAM for aggressive DVS down to 0.57 V","authors":"Jinwook Jung, Y. Nakata, S. Okumura, H. Kawaguchi, M. Yoshimoto","doi":"10.1109/ICECS.2011.6122328","DOIUrl":"https://doi.org/10.1109/ICECS.2011.6122328","url":null,"abstract":"This paper presents a dependable cache memory for which associativity can be reconfigured dynamically. The proposed associativity-reconfigurable cache consists of pairs of cache ways. Each pair has two modes: the normal mode and the dependable mode. The proposed cache can dynamically enhance its reliability in the dependable mode, thereby trading off its performance. The reliability of the proposed cache can be scaled by reconfiguring its associativity. Moreover, the configuration can be chosen based upon current operating conditions. Our chip measurement results show that the proposed dependable cache possesses the scalable characteristic of reliability. Moreover, it can decrease the minimum operating voltage by 115 mV. The cycle accurate simulation shows that designing the L1, L2 caches using the proposed scheme results in 4.93% IPC loss on average. Area estimation results show that the proposed cache adds area overhead of 1.91% and 5.57% in 32-KB and 256-KB caches, respectively.","PeriodicalId":251525,"journal":{"name":"2011 18th IEEE International Conference on Electronics, Circuits, and Systems","volume":"33 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2011-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114641544","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 5
A non-linear control of electric vehicle driven by induction motors 感应电机驱动电动汽车的非线性控制
2011 18th IEEE International Conference on Electronics, Circuits, and Systems Pub Date : 2011-12-01 DOI: 10.1109/ICECS.2011.6122363
Bekkouche Djamal-Dine, H. Khalid, Bouhamida Mohammed, Benabdellah Tewfik
{"title":"A non-linear control of electric vehicle driven by induction motors","authors":"Bekkouche Djamal-Dine, H. Khalid, Bouhamida Mohammed, Benabdellah Tewfik","doi":"10.1109/ICECS.2011.6122363","DOIUrl":"https://doi.org/10.1109/ICECS.2011.6122363","url":null,"abstract":"We present in this paper a new asymptotically stable scheme for motion control of Electric Vehicle with induction motor drives. The result is established considering a model that includes the electrical and mechanical dynamics of the induction motors, as well as the full body dynamics of high speed Electric Vehicle. The procedures we will follow consist of four steps. First, we design an inner control loop such that the overall System becomes a cascade connection of two nonlinear subsystems, i.e., the motor electrical dynamics and the electrical vehicle mechanical system as load. The output of the first subsystem, that is the generated torque, drives the electrical vehicle dynamics, and the other cross coupling are removed. Second, the torque required to track the desired wheel trajectory is evaluated by passivity approach. Third, we define a desired current behavior which reflects an objective of attaining field orientation. Four, we design a controller that insures the torques generated by the motors asymptotically track the desired torque. Parameters of electrical vehicle and motors are known. The local stability is obtained for controller with the nonlinear observer of rotor motor currents. Simulation results are presented with a electrical vehicle in Matlab-Simulink to illustrate the performance of the control law.","PeriodicalId":251525,"journal":{"name":"2011 18th IEEE International Conference on Electronics, Circuits, and Systems","volume":"14 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2011-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116186069","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
A self-sufficient digitally controlled ring oscillator compensated for supply voltage variation 一个自给自足的数字控制环形振荡器补偿电源电压变化
2011 18th IEEE International Conference on Electronics, Circuits, and Systems Pub Date : 2011-12-01 DOI: 10.1109/ICECS.2011.6122318
M. Terosiet, S. Feruglio, F. Vallette, P. Garda, O. Romain, J. Kernec
{"title":"A self-sufficient digitally controlled ring oscillator compensated for supply voltage variation","authors":"M. Terosiet, S. Feruglio, F. Vallette, P. Garda, O. Romain, J. Kernec","doi":"10.1109/ICECS.2011.6122318","DOIUrl":"https://doi.org/10.1109/ICECS.2011.6122318","url":null,"abstract":"A self-sufficient Giga-Hertz digitally controlled ring oscillator for clock distribution network is presented in this paper. It features a high supply insensitivity in order to mitigate the additional jitter due to supply noise. This is achieved by inducing a mutual compensation between the oscillation frequency parameters that are affected by the supply voltage variations. The proposed method can be easily implemented and takes advantage of the deep sub-micrometer effects peculiar to topical CMOS technologies. We demonstrate by simulations that this approach remains efficient over process variations despite the reliability issue of short channel MOS transistors.","PeriodicalId":251525,"journal":{"name":"2011 18th IEEE International Conference on Electronics, Circuits, and Systems","volume":"56 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2011-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126534399","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 2
System-level energy estimation with Powersim 系统级能量估计与Powersim
2011 18th IEEE International Conference on Electronics, Circuits, and Systems Pub Date : 2011-12-01 DOI: 10.1109/ICECS.2011.6122376
Marco Giammarini, M. Conti, S. Orcioni
{"title":"System-level energy estimation with Powersim","authors":"Marco Giammarini, M. Conti, S. Orcioni","doi":"10.1109/ICECS.2011.6122376","DOIUrl":"https://doi.org/10.1109/ICECS.2011.6122376","url":null,"abstract":"The present paper proposes a SystemC class library aimed to the calculation of energy consumption of hardware described at system level. To this end C++ operators are monitored and different energy models are used for each data type. This method does not require any change in the application source code. An application example with measures is proposed.","PeriodicalId":251525,"journal":{"name":"2011 18th IEEE International Conference on Electronics, Circuits, and Systems","volume":"39 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2011-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126562560","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 23
FPGA-implementation of high-speed MLP neural network 高速MLP神经网络的fpga实现
2011 18th IEEE International Conference on Electronics, Circuits, and Systems Pub Date : 2011-12-01 DOI: 10.1109/ICECS.2011.6122304
M. Bahoura, Chan-Wang Park
{"title":"FPGA-implementation of high-speed MLP neural network","authors":"M. Bahoura, Chan-Wang Park","doi":"10.1109/ICECS.2011.6122304","DOIUrl":"https://doi.org/10.1109/ICECS.2011.6122304","url":null,"abstract":"This paper presents a new high-speed FPGA implementation of a pipelined adaptive multilayer perceptron (MLP). The proposed approach is a fully parallel architecture based on the delayed backpropagation algorithm, which permits to reduce the critical path and consequently increases the operating frequency. Results obtained with nonlinear function approximation show that this pipelined parallel architecture is four times faster than the conventional one.","PeriodicalId":251525,"journal":{"name":"2011 18th IEEE International Conference on Electronics, Circuits, and Systems","volume":"9 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2011-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125724326","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 31
Configurable baseband digital transceiver for Gbps wireless 60 GHz communications 可配置基带数字收发器，用于Gbps无线60 GHz通信
2011 18th IEEE International Conference on Electronics, Circuits, and Systems Pub Date : 2011-12-01 DOI: 10.1109/ICECS.2011.6122246
D. Diamantopoulos, Panagiotis Galiatsatos, A. Karachalios, G. Lentaris, D. Reisis, D. Soudris
{"title":"Configurable baseband digital transceiver for Gbps wireless 60 GHz communications","authors":"D. Diamantopoulos, Panagiotis Galiatsatos, A. Karachalios, G. Lentaris, D. Reisis, D. Soudris","doi":"10.1109/ICECS.2011.6122246","DOIUrl":"https://doi.org/10.1109/ICECS.2011.6122246","url":null,"abstract":"The evolution of 60 GHz wireless networks using Orthogonal Frequency Division Multiplexing (OFDM) technique imposed requirements of increased processing in the baseband implementations. The current paper focuses on the design of a pipelined architecture realizing the baseband functions. The design bases on using parallel paths to achieve a throughput of 1.6 Gbps. The number of paths is configured at compile time to be 4, 8 or 16, for achieving maximal throughput by either using cutting edge technology FPGA platforms or target implementations with low cost devices. FPGA implementations validate the results.","PeriodicalId":251525,"journal":{"name":"2011 18th IEEE International Conference on Electronics, Circuits, and Systems","volume":"2013 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2011-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131348714","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 4
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