FPGA-implementation of high-speed MLP neural network

M. Bahoura, Chan-Wang Park
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引用次数: 31

Abstract

This paper presents a new high-speed FPGA implementation of a pipelined adaptive multilayer perceptron (MLP). The proposed approach is a fully parallel architecture based on the delayed backpropagation algorithm, which permits to reduce the critical path and consequently increases the operating frequency. Results obtained with nonlinear function approximation show that this pipelined parallel architecture is four times faster than the conventional one.
高速MLP神经网络的fpga实现
本文提出了一种新的高速FPGA实现流水线自适应多层感知器(MLP)。该方法是一种基于延迟反向传播算法的全并行架构,可以减少关键路径,从而提高工作频率。非线性函数逼近的结果表明,这种流水线并行结构的速度是传统并行结构的4倍。
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