D. Diamantopoulos, Panagiotis Galiatsatos, A. Karachalios, G. Lentaris, D. Reisis, D. Soudris
{"title":"Configurable baseband digital transceiver for Gbps wireless 60 GHz communications","authors":"D. Diamantopoulos, Panagiotis Galiatsatos, A. Karachalios, G. Lentaris, D. Reisis, D. Soudris","doi":"10.1109/ICECS.2011.6122246","DOIUrl":null,"url":null,"abstract":"The evolution of 60 GHz wireless networks using Orthogonal Frequency Division Multiplexing (OFDM) technique imposed requirements of increased processing in the baseband implementations. The current paper focuses on the design of a pipelined architecture realizing the baseband functions. The design bases on using parallel paths to achieve a throughput of 1.6 Gbps. The number of paths is configured at compile time to be 4, 8 or 16, for achieving maximal throughput by either using cutting edge technology FPGA platforms or target implementations with low cost devices. FPGA implementations validate the results.","PeriodicalId":251525,"journal":{"name":"2011 18th IEEE International Conference on Electronics, Circuits, and Systems","volume":"2013 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2011-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"4","resultStr":null,"platform":"Semanticscholar","paperid":null,"PeriodicalName":"2011 18th IEEE International Conference on Electronics, Circuits, and Systems","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/ICECS.2011.6122246","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 4
Abstract
The evolution of 60 GHz wireless networks using Orthogonal Frequency Division Multiplexing (OFDM) technique imposed requirements of increased processing in the baseband implementations. The current paper focuses on the design of a pipelined architecture realizing the baseband functions. The design bases on using parallel paths to achieve a throughput of 1.6 Gbps. The number of paths is configured at compile time to be 4, 8 or 16, for achieving maximal throughput by either using cutting edge technology FPGA platforms or target implementations with low cost devices. FPGA implementations validate the results.