{"title":"Maximal diagnosis of interconnects of random access memories","authors":"Jun Zhao, F. Meyer, F. Lombardi, N. Park","doi":"10.1109/VTEST.1999.766692","DOIUrl":"https://doi.org/10.1109/VTEST.1999.766692","url":null,"abstract":"This paper presents an approach for the maximal diagnosis of all faults (stuck-at, open and short) in the interconnect of a random access memory (RAM); the interconnect includes data and address lines. This approach accomplishes maximal diagnosis under a complex model in which the lines in the interconnect of the RAM are involved in multiple faults simultaneously. The proposed algorithm (referred to as the Improved Maximal Diagnosis Algorithm, or IMDA) requires max{n,m-I}+n+3 WRITE and max{n,m}+2n READ, where n is the number of address lines and m is the number of data lines.","PeriodicalId":248104,"journal":{"name":"Proceedings 17th IEEE VLSI Test Symposium (Cat. No.PR00146)","volume":"55 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1999-04-26","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126659067","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"Specification back-propagation and its application to DC fault simulation for analog/mixed-signal circuits","authors":"Jiun-Lang Huang, Chen-Yang Pan, K. Cheng","doi":"10.1109/VTEST.1999.766669","DOIUrl":"https://doi.org/10.1109/VTEST.1999.766669","url":null,"abstract":"In this paper we present the specification backpropagation technique which enables one to derive the constraint of an internal functional block with respect to a given DC specification for an analog/mixed-signal system. Based on this technique, we implement an efficient fault simulator which reduces the required efforts by (1) removing undetectable faults from the fault list, and (2) performing fault simulation only locally for the fault block. Simulation results on an industrial design show a speedup factor of 7.2 with 98% correct classification of detected and undetected faults as compared with full-chip DC fault simulation.","PeriodicalId":248104,"journal":{"name":"Proceedings 17th IEEE VLSI Test Symposium (Cat. No.PR00146)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1999-04-26","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115357028","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"Test metrics for analog parametric faults","authors":"S. Sunter, N. Nagi","doi":"10.1109/VTEST.1999.766670","DOIUrl":"https://doi.org/10.1109/VTEST.1999.766670","url":null,"abstract":"This paper first summarizes the complete range of analog defects and resultant faults. A complete set of metrics is then derived for measuring the quality of analog tests. The probability-based equations for fault coverage, defect level, yield coverage, and yield loss are self-consistent, and consistent with existing equations for digital test metrics. We introduce the concept of partial coverage, show that it is inherent to analog testing, and show that coverage cannot be calculated without knowing the performance specifications for a circuit, as well as the process parameter distributions. Practical methods for calculating probabilities are discussed, and simple, illustrative examples given.","PeriodicalId":248104,"journal":{"name":"Proceedings 17th IEEE VLSI Test Symposium (Cat. No.PR00146)","volume":"32 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1999-04-26","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132548930","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
P. Girard, Loïs Guiller, C. Landrault, S. Pravossoudovitch
{"title":"A test vector inhibiting technique for low energy BIST design","authors":"P. Girard, Loïs Guiller, C. Landrault, S. Pravossoudovitch","doi":"10.1109/VTEST.1999.766696","DOIUrl":"https://doi.org/10.1109/VTEST.1999.766696","url":null,"abstract":"During self-test, the switching activity of the circuit under test is significantly increased compared to normal operation and leads to an increased power consumption which often exceeds specified limits. In the first part of this paper, we propose a test vector inhibiting technique which tackles the increased activity during test operation. Next, a mixed solution based on a reseeding scheme and the vector inhibiting technique is proposed to deal with hard-to-test circuits that contain pseudo-random resistant faults. From a general point of view, the goal of these techniques is to minimize the total energy consumption during test and to allow the test at system speed in order to achieve high fault coverage. The effectiveness of the proposed low energy BIST scheme has been validated on a set of benchmarks with respect to hardware overhead and power savings.","PeriodicalId":248104,"journal":{"name":"Proceedings 17th IEEE VLSI Test Symposium (Cat. No.PR00146)","volume":"159 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1999-04-26","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132421820","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"Behavioral fault modeling in a VHDL synthesis environment","authors":"R. Hayne, Barry W. Johnson","doi":"10.1109/VTEST.1999.766684","DOIUrl":"https://doi.org/10.1109/VTEST.1999.766684","url":null,"abstract":"This paper proposes new fault models for VHDL behavioral descriptions of combinational logic circuits. The models are developed via abstraction of industry standard single-stuck-line (SSL) faults into the behavioral domain. A functional analysis technique is used to evaluate the effects of SSL faults on gate level implementations. Generalized functional faults are then abstracted into the behavioral domain by examining their relationship with the higher level language construct. Test vectors derived from the new behavioral fault models are applied to synthesized gate level realizations of an example arithmetic logic unit. Resulting gate level fault coverage is determined and used as a measure of effectiveness for the new fault models. Because the behavioral faults are derived from a functional analysis of low level faults, they provide improved fault coverage over previous fault models.","PeriodicalId":248104,"journal":{"name":"Proceedings 17th IEEE VLSI Test Symposium (Cat. No.PR00146)","volume":"70 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1999-04-26","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132830818","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"Time redundancy based soft-error tolerance to rescue nanometer technologies","authors":"M. Nicolaidis","doi":"10.1109/VTEST.1999.766651","DOIUrl":"https://doi.org/10.1109/VTEST.1999.766651","url":null,"abstract":"The increased operating frequencies, geometry shrinking and power supply reduction that accompany the process of very deep submicron scaling, affect the reliable operation of very deep submicron ICs. The effects of various noise sources are becoming of great concern. In particularly, it is predicted that single event upsets induced by alpha particles and cosmic radiation will become a cause of unacceptable error rates in future very deep submicron and nanometer technologies. This problem, concerning in the past more often parts used in space, will affect future ICs at sea level. This challenging problem has to be solved otherwise technological progress will be blocked soon. Thus, fault tolerant design is becoming necessary, even for commodity applications. But economic constraints of commodity applications exclude the use of traditional, high-cost fault tolerant techniques. This work uses time redundancy techniques to derive low cost soft-error tolerant implementations for logic networks.","PeriodicalId":248104,"journal":{"name":"Proceedings 17th IEEE VLSI Test Symposium (Cat. No.PR00146)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1999-04-26","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115513377","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"Testing high speed VLSI devices using slower testers","authors":"Angela Krstic, K. Cheng, S. Chakradhar","doi":"10.1109/VTEST.1999.766641","DOIUrl":"https://doi.org/10.1109/VTEST.1999.766641","url":null,"abstract":"The speed of new VLSI designs is rapidly increasing. Assuring the performance of the circuit requires that the circuit be tested at its intended operating speed. The high cost of high speed testers makes it impossible for the testers to follow the designs in terms of speed increase. This gap between the speed of the new circuits and the speed of the testers is not likely to disappear. In this paper, we focus on at-speed strategies for testing high speed designs on slower testers. Conventional at-speed testing strategies assume that the primary inputs/outputs can be applied/observed at the circuit rated speed. This requires a high speed tester. Our assumption is that a fast clock matching the speed of the designs is available. We describe two classes of at-speed strategies that can be used on a low speed tester. The first class consists of testing schemes for which the test generation procedure is independent of the speed of the tester. These methods apply multiple input patterns in one tester cycle and the test application time for them can be long. The strategies in the second class of at-speed testing schemes integrate the tester's speed limitations with the test generation process. Due to constraints placed at the test generation process, these schemes might result in a reduced fault coverage. To increase the fault coverage and reduce the test application time, the slow-fast-slow and at-speed strategies can be combined for testing high speed designs on slower testers. We present preliminary experimental results for at-speed schemes for slow testers for transition faults.","PeriodicalId":248104,"journal":{"name":"Proceedings 17th IEEE VLSI Test Symposium (Cat. No.PR00146)","volume":"100 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1999-04-26","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122424805","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"RT-level TPG exploiting high-level synthesis information","authors":"S. Chiusano, Fulvio Corno, P. Prinetto","doi":"10.1109/VTEST.1999.766685","DOIUrl":"https://doi.org/10.1109/VTEST.1999.766685","url":null,"abstract":"High-level test pattern generation is today a widely investigated research topic. The present paper proposes a fully automated, simulation-based ATPG system, to address test pattern generation for circuits described at the RT-level. The approach is based on a set of suitable testability metrics, and the test pattern generation phase resorts to genetic algorithms. Experiments show the excellent fault coverage provided by the RT-level test patterns, when applied at the final gate-level. The approach, being based on a high-level representation, promises to be particularly suited where gate-level ATPGs are often inefficient, mainly for large circuits and for control-intensive designs.","PeriodicalId":248104,"journal":{"name":"Proceedings 17th IEEE VLSI Test Symposium (Cat. No.PR00146)","volume":"249 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1999-04-26","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121130917","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"On n-detection test sets and variable n-detection test sets for transition faults","authors":"I. Pomeranz, S. Reddy","doi":"10.1109/VTEST.1999.766662","DOIUrl":"https://doi.org/10.1109/VTEST.1999.766662","url":null,"abstract":"We study the effectiveness of n-detection test sets based on transition faults in detecting defects that affect the timing behavior of a circuit. We use path delay faults as surrogates for unmodeled defects, and show that the path delay fault coverage achieved by an n-detection transition fault test set increases significantly as n is increased. We also introduce a method to reduce the number of tests included in an n-detection test set by using different values of n for different faults based on their potential effect on the defect coverage. The resulting test sets are referred to as variable n-detection test sets.","PeriodicalId":248104,"journal":{"name":"Proceedings 17th IEEE VLSI Test Symposium (Cat. No.PR00146)","volume":"72 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1999-04-26","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126310328","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
R. Kapur, B. Keller, B. Koenemann, M. Lousberg, P. Reuter, T. Taylor, P. Varma
{"title":"P1500-CTL: Towards a Standard Core Test Language","authors":"R. Kapur, B. Keller, B. Koenemann, M. Lousberg, P. Reuter, T. Taylor, P. Varma","doi":"10.1109/VTEST.1999.766708","DOIUrl":"https://doi.org/10.1109/VTEST.1999.766708","url":null,"abstract":"As part of the IEEE standardization activities of P1500, a language is being defined for embedded core test to enable the reuse of intellectual property in a system on a chip environment. A Core Test Description Language (CTL) is being proposed as an industry standard method for capturing and expressing test related information for reusable cores. This paper discusses the scope of the standardization activity.","PeriodicalId":248104,"journal":{"name":"Proceedings 17th IEEE VLSI Test Symposium (Cat. No.PR00146)","volume":"53 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1999-04-25","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133812349","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}