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Proceedings 17th IEEE VLSI Test Symposium (Cat. No.PR00146)最新文献

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A systematic DFT procedure for library cells 库单元的系统DFT程序
Proceedings 17th IEEE VLSI Test Symposium (Cat. No.PR00146) Pub Date : 1999-04-26 DOI: 10.1109/VTEST.1999.766704
Jingjing Xu, R. Kundu, F. Ferguson
{"title":"A systematic DFT procedure for library cells","authors":"Jingjing Xu, R. Kundu, F. Ferguson","doi":"10.1109/VTEST.1999.766704","DOIUrl":"https://doi.org/10.1109/VTEST.1999.766704","url":null,"abstract":"We present an automated procedure for improving the testability of a product by improving the testability of cells in the cell library. This method was applied to a scan flip-flop from Cyrix's standard cell library. Based on this analysis, some design and layout changes were suggested, which brought down the probability of difficult-to-detect faults by 70%, without compromising the performance or increasing the area of the circuit.","PeriodicalId":248104,"journal":{"name":"Proceedings 17th IEEE VLSI Test Symposium (Cat. No.PR00146)","volume":"221 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1999-04-26","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122866994","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 13
Evaluating the fault tolerance capabilities of embedded systems via BDM 基于BDM的嵌入式系统容错能力评估
Proceedings 17th IEEE VLSI Test Symposium (Cat. No.PR00146) Pub Date : 1999-04-26 DOI: 10.1109/VTEST.1999.766703
M. Rebaudengo, M. Reorda
{"title":"Evaluating the fault tolerance capabilities of embedded systems via BDM","authors":"M. Rebaudengo, M. Reorda","doi":"10.1109/VTEST.1999.766703","DOIUrl":"https://doi.org/10.1109/VTEST.1999.766703","url":null,"abstract":"Fault injection is a viable solution for verifying the correct design and implementation of fault tolerance mechanisms at different levels (hardware and software). The paper discusses the use of the background diagnostic mode (BDM), available on several Motorola microprocessors and microcontrollers, for implementing a fault injection environment. BDM is well suited to implement some of the most critical operations required by a fault injection environment, such as activating the injection procedure, injecting the fault in memory or registers, and observing the faulty system behavior. The characteristics of a BDM-based fault injection environment in terms of intrusiveness, flexibility, time efficiency, and system requirements are analyzed. The authors exploit a prototypical environment they implemented to validate this analysis. As a result, the approach appears to be well suited for implementing low-cost fault injection experiments on simple embedded microprocessor- and microcontroller-based boards. Some limitations are also outlined, mostly in terms of execution time slow-down.","PeriodicalId":248104,"journal":{"name":"Proceedings 17th IEEE VLSI Test Symposium (Cat. No.PR00146)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1999-04-26","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130488062","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 30
A new bare die test methodology 一种新的裸模试验方法
Proceedings 17th IEEE VLSI Test Symposium (Cat. No.PR00146) Pub Date : 1999-04-26 DOI: 10.1109/VTEST.1999.766678
Zao Yang, K. Cheng, K. Tai
{"title":"A new bare die test methodology","authors":"Zao Yang, K. Cheng, K. Tai","doi":"10.1109/VTEST.1999.766678","DOIUrl":"https://doi.org/10.1109/VTEST.1999.766678","url":null,"abstract":"While multichip module technology has been developed for high performance IC applications, the technology is not widely adopted due to economical reasons. One of the reasons that makes the technology economically unattractive is the problems and the high cost associated with testing and diagnosing each individual un-packaged IC in the system and the MCM module itself. The low MCM system yield prevents the technology from being used other than in high cost and high performance applications. In this paper, we propose a new methodology using ideas of tester-on-a-chip and a pressure contact technology to test bare dies. This methodology can reduce the IC testing cost and overall cost of the MCM module. It can also be considered as an alternative to high speed wafer probe. We designed an experiment for SRAM dies to examine the feasibility of this new method.","PeriodicalId":248104,"journal":{"name":"Proceedings 17th IEEE VLSI Test Symposium (Cat. No.PR00146)","volume":"58 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1999-04-26","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127774431","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 3
Weight-based codes and their application to concurrent error detection of multilevel circuits 权重码及其在多电平电路并发错误检测中的应用
Proceedings 17th IEEE VLSI Test Symposium (Cat. No.PR00146) Pub Date : 1999-04-26 DOI: 10.1109/VTEST.1999.766691
D. Das, N. Touba
{"title":"Weight-based codes and their application to concurrent error detection of multilevel circuits","authors":"D. Das, N. Touba","doi":"10.1109/VTEST.1999.766691","DOIUrl":"https://doi.org/10.1109/VTEST.1999.766691","url":null,"abstract":"This paper proposes a new class of codes termed \"weight-based codes\" where each output bit is assigned a weight and the check bits represent the stem of the weights of the output bits which have value \"1\". A Berger code is a special member of this proposed class of codes where each output bit is assigned a weight of one. This paper describes the application of these codes for the efficient on-line error detection of arbitrary multilevel circuits. The overall probability of detecting any number of erroneous bits at the output caused by a single internal fault is shown to be higher for weight-based codes than standard error detecting codes. Further, a very efficient design exists for the checker. The checker is area and speed efficient, has low power consumption, and can be tested by a small set of incoming code words. There is always a tradeoff between the fault detection capability and area overhead requirement of an error detecting code. Weight-based codes present a controlled way of increasing the number of check bits to achieve a desired fault detection capability.","PeriodicalId":248104,"journal":{"name":"Proceedings 17th IEEE VLSI Test Symposium (Cat. No.PR00146)","volume":"106 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1999-04-26","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128127804","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 62
Techniques to encode and compress fault dictionaries 编码和压缩错误字典的技术
Proceedings 17th IEEE VLSI Test Symposium (Cat. No.PR00146) Pub Date : 1999-04-26 DOI: 10.1109/VTEST.1999.766665
S. Chakravarty, V. Gopal
{"title":"Techniques to encode and compress fault dictionaries","authors":"S. Chakravarty, V. Gopal","doi":"10.1109/VTEST.1999.766665","DOIUrl":"https://doi.org/10.1109/VTEST.1999.766665","url":null,"abstract":"Dictionary encoding schemes have not addressed the cost of reconstructing the dictionary during fault location. We show that by modifying a previously proposed dictionary encoding scheme only small portions of the information need be reconstructed during fault location. This provides a mechanism to reduce the number of secondary accesses during fault location. For pass-fail dictionaries, we present a simplified encoding scheme that reduces both the secondary storage requirement as well as the number of secondary accesses. A novel dictionary structure, known as hybrid dictionaries, which retains the full resolution with respect to modeled faults is presented. Heuristics to compute such dictionaries, its usefulness and how such dictionaries can be encoded for quick information retrieval are discussed.","PeriodicalId":248104,"journal":{"name":"Proceedings 17th IEEE VLSI Test Symposium (Cat. No.PR00146)","volume":"41 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1999-04-26","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114977739","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 16
A flexible path selection procedure for path delay fault testing 一种用于路径延迟故障检测的灵活路径选择程序
Proceedings 17th IEEE VLSI Test Symposium (Cat. No.PR00146) Pub Date : 1999-04-26 DOI: 10.1109/VTEST.1999.766659
I. Pomeranz, S. Reddy
{"title":"A flexible path selection procedure for path delay fault testing","authors":"I. Pomeranz, S. Reddy","doi":"10.1109/VTEST.1999.766659","DOIUrl":"https://doi.org/10.1109/VTEST.1999.766659","url":null,"abstract":"We describe a path selection procedure that selects target faults for path delay fault test generation. Since large numbers of path delay faults may be untestable, the proposed procedure does not select a fixed set of paths. Instead, it provides compactly represented subsets of paths, referred to as super-paths, and allows the test generation procedure to select one path out of each subset based on testability considerations.","PeriodicalId":248104,"journal":{"name":"Proceedings 17th IEEE VLSI Test Symposium (Cat. No.PR00146)","volume":"56 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1999-04-26","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125050722","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 7
On testing of non-isolated embedded legacy cores and their surround logic 非隔离嵌入式遗留核及其环绕逻辑的测试
Proceedings 17th IEEE VLSI Test Symposium (Cat. No.PR00146) Pub Date : 1999-04-26 DOI: 10.1109/VTEST.1999.766645
I. Pomeranz, Y. Zorian
{"title":"On testing of non-isolated embedded legacy cores and their surround logic","authors":"I. Pomeranz, Y. Zorian","doi":"10.1109/VTEST.1999.766645","DOIUrl":"https://doi.org/10.1109/VTEST.1999.766645","url":null,"abstract":"We consider issues related to the testing of a legacy core embedded in user-defined logic. We assume that the only information available about the core is its test set. We provide procedures for testing the core and its surrounding logic without adding DFT logic. The procedures maximize the information extracted from the test set given for the core, in order to maximize the fault coverage achieved without DFT. We also describe DFT insertion procedures. The core and the surrounding logic are considered simultaneously during DFT insertion to minimize the amount of DFT logic required.","PeriodicalId":248104,"journal":{"name":"Proceedings 17th IEEE VLSI Test Symposium (Cat. No.PR00146)","volume":"224 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1999-04-26","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127188771","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 8
PADded cache: a new fault-tolerance technique for cache memories 填充缓存:一种新的缓存容错技术
Proceedings 17th IEEE VLSI Test Symposium (Cat. No.PR00146) Pub Date : 1999-04-26 DOI: 10.1109/VTEST.1999.766701
P. Shirvani, E. McCluskey
{"title":"PADded cache: a new fault-tolerance technique for cache memories","authors":"P. Shirvani, E. McCluskey","doi":"10.1109/VTEST.1999.766701","DOIUrl":"https://doi.org/10.1109/VTEST.1999.766701","url":null,"abstract":"This paper presents a new fault-tolerance technique for cache memories. Current fault-tolerance techniques for caches are limited either by the number of faults that can be tolerated or by the rapid degradation of performance as the number of faults increases. In this paper, we present a new technique that overcomes these two problems. This technique uses a special Programmable Address Decoder (PAD) to disable faulty blocks and to re-map their references to healthy blocks. Simulation results show that the performance degradation of direct-mapped caches with PAD is smaller than the previous techniques. However, for set-associative caches, the overhead of PAD is primarily advantageous if a relatively large number of faults is to be tolerated. The area overhead was estimated at about 10% of the overall cache area for a hypothetical design and is expected to be less for actual designs. The access time overhead is negligible.","PeriodicalId":248104,"journal":{"name":"Proceedings 17th IEEE VLSI Test Symposium (Cat. No.PR00146)","volume":"101 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1999-04-26","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130192082","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 93
Defect-oriented Verilog fault simulation of SoC macros using a stratified fault sampling technique 基于分层故障采样技术的面向缺陷的SoC宏Verilog故障仿真
Proceedings 17th IEEE VLSI Test Symposium (Cat. No.PR00146) Pub Date : 1999-04-26 DOI: 10.1109/VTEST.1999.766683
Marcelino B. Santos, F. Gonçalves, I. Teixeira, João Paulo Teixeira
{"title":"Defect-oriented Verilog fault simulation of SoC macros using a stratified fault sampling technique","authors":"Marcelino B. Santos, F. Gonçalves, I. Teixeira, João Paulo Teixeira","doi":"10.1109/VTEST.1999.766683","DOIUrl":"https://doi.org/10.1109/VTEST.1999.766683","url":null,"abstract":"The validation of high-quality tests requires defect-oriented (DO) fault simulation. The purpose of this paper is to propose a methodology for mixed-level DO Verilog fault simulation. A novel tool, veriDOF, is introduced. Structural zooming is performed only for the system module in which the faults are injected. Verilog models for bridging and line open defects are proposed for intra-gate and inter-gate faults, using a pre-computed test view of each library cell. A stratified fault sampling technique is used to boost the computational efficiency of the new tool. Results are presented for ISCAS benchmarks and a public domain processor, PIC.","PeriodicalId":248104,"journal":{"name":"Proceedings 17th IEEE VLSI Test Symposium (Cat. No.PR00146)","volume":"55 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1999-04-26","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132312602","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 20
A digital BIST for operational amplifiers embedded in mixed-signal circuits 一种用于嵌入在混合信号电路中的运算放大器的数字BIST
Proceedings 17th IEEE VLSI Test Symposium (Cat. No.PR00146) Pub Date : 1999-04-26 DOI: 10.1109/VTEST.1999.766680
I. Rayane, J. Velasco-Medina, M. Nicolaidis
{"title":"A digital BIST for operational amplifiers embedded in mixed-signal circuits","authors":"I. Rayane, J. Velasco-Medina, M. Nicolaidis","doi":"10.1109/VTEST.1999.766680","DOIUrl":"https://doi.org/10.1109/VTEST.1999.766680","url":null,"abstract":"A new digital BIST structure is proposed in this paper. During test mode, the op amp under test is placed in a voltage follower configuration in order to detect its slew-rate deviation, or in a comparator configuration in order to detect its signal propagation delay deviation. The test stimuli and the BIST control signals are simply derived from the test control signal TST using delay elements and logical gates. The test response is analyzed by using pure digital circuitry. Simulation results show the effectiveness of the proposed technique with a low area overhead.","PeriodicalId":248104,"journal":{"name":"Proceedings 17th IEEE VLSI Test Symposium (Cat. No.PR00146)","volume":"214 0 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1999-04-26","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125523010","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 27
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