Proceedings 17th IEEE VLSI Test Symposium (Cat. No.PR00146)最新文献_第2页

A test point insertion algorithm for mixed-signal circuits 混合信号电路的测试点插入算法

Proceedings 17th IEEE VLSI Test Symposium (Cat. No.PR00146) Pub Date : 1999-04-26 DOI: 10.1109/VTEST.1999.766682

Jinyan Zhang, S. Huynh, M. Soma

引用次数: 15

Instruction-driven wake-up mechanisms for Snoopy TAP controller 指令驱动的唤醒机制史努比TAP控制器

Proceedings 17th IEEE VLSI Test Symposium (Cat. No.PR00146) Pub Date : 1999-04-26 DOI: 10.1109/VTEST.1999.766705

D. Bhattacharya

{"title":"Instruction-driven wake-up mechanisms for Snoopy TAP controller","authors":"D. Bhattacharya","doi":"10.1109/VTEST.1999.766705","DOIUrl":"https://doi.org/10.1109/VTEST.1999.766705","url":null,"abstract":"The issue of handling multiple embedded 1149.1-compliant TAP controllers (as part of embedded cores) in a 1149.1-compliant IC, has received significant attention, in recent times. The Hierarchical TAP (HTAP) architecture, previously developed by this author, provides a systematic solution to this problem, by allowing multiple embedded TAPs to share one set of 1149.1-specified test pins on the IC. The HTAP architecture requires an augmented version of the 1149.1-specified TAP-designated the Snoopy TAP (SNTAP)-in the top-level of the design hierarchy, that handles 1149.1-specified TAP functions for the non-TAP'ed parts of the IC, and performs arbitration of the shared IC pins between multiple embedded TAPs. Previously, a mechanism was developed to wake up the SNTAP using a simple string of constant values (0 or 1) on the TMS input. Two new mechanisms to wake up SNTAP by means of an instruction scanned in, are described in this report. Both mechanisms allow embedded 1149.1-compliant TAP's to be used in a hierarchical design, as is, without any hardware modification. Moreover, both mechanisms enable reuse of the test program from the embedded TAP'ed cores, without any modification. The instructions to wake up the SNTAP-to switch access to different TAP-ed cores-can be simply inserted in-between the test programs for the embedded cores.","PeriodicalId":248104,"journal":{"name":"Proceedings 17th IEEE VLSI Test Symposium (Cat. No.PR00146)","volume":"12 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1999-04-26","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132352596","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 4

On the evaluation of arbitrary defect coverage of test sets 关于测试集任意缺陷覆盖率的评估

Proceedings 17th IEEE VLSI Test Symposium (Cat. No.PR00146) Pub Date : 1999-04-26 DOI: 10.1109/VTEST.1999.766699

Ankur Jain, M. Hsiao, V. Boppana, M. Fujita

引用次数: 5

Instruction randomization self test for processor cores 处理器核心的指令随机自检

Proceedings 17th IEEE VLSI Test Symposium (Cat. No.PR00146) Pub Date : 1999-04-26 DOI: 10.1109/VTEST.1999.766644

Ken W. Batcher, C. Papachristou

引用次数: 125

Built-in current sensor for IDDQ testing in deep submicron CMOS 内置电流传感器在深亚微米CMOS IDDQ测试

Proceedings 17th IEEE VLSI Test Symposium (Cat. No.PR00146) Pub Date : 1999-04-26 DOI: 10.1109/VTEST.1999.766657

T. Calin, L. Anghel, M. Nicolaidis

引用次数: 11

TAO-BIST: a framework for testability analysis and optimization of RTL circuits for BIST TAO-BIST:一个用于BIST RTL电路可测试性分析和优化的框架

Proceedings 17th IEEE VLSI Test Symposium (Cat. No.PR00146) Pub Date : 1999-04-26 DOI: 10.1109/VTEST.1999.766695

S. Ravi, G. Lakshminarayana, N. Jha

{"title":"TAO-BIST: a framework for testability analysis and optimization of RTL circuits for BIST","authors":"S. Ravi, G. Lakshminarayana, N. Jha","doi":"10.1109/VTEST.1999.766695","DOIUrl":"https://doi.org/10.1109/VTEST.1999.766695","url":null,"abstract":"In this paper, we present TAO-BIST, a framework for testing register-transfer level (RTL) controller-datapath circuits using built-in self-test (BIST). Conventional BIST techniques at the RTL generally introduce more testability hardware than is necessary, thereby causing unnecessary area, delay and power overheads. They have typically been applied to only application-specific integrated circuits (ASICs). TAO-BIST adopts a three-phased approach to provide an efficient BIST framework at the RTL. In the first phase, we identify and add an initial set of test enhancements to the given circuit. In the second phase, we use regular-expression based high-level symbolic testability analysis of a BIST model of the circuit to completely encapsulate justification/propagation information for the modules under test. The regular expressions so obtained are then used to construct a Boolean function in the final phase for determining a test enhancement solution that meets delay constraints with minimal area overheads. Our method is applicable to a wide spectrum of circuits including ASICs, application-specific programmable processors (ASPPs), application-specific instruction processors (ASIPs), digital signal processors (DSPs) and microprocessors. Experimental results on a number of benchmark circuits show that high fault coverage (>99%) can be obtained with our scheme. The average area and delay overheads due to TAO-BIST are only 6.0%, and 1.5%, respectively. The test application time to achieve the high fault coverage for the whole controller-datapath circuit is also quite low.","PeriodicalId":248104,"journal":{"name":"Proceedings 17th IEEE VLSI Test Symposium (Cat. No.PR00146)","volume":"23 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1999-04-26","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122648874","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 11

Built-in test pattern generation for high-performance circuits using twisted-ring counters 内置测试模式生成高性能电路使用扭环计数器

Proceedings 17th IEEE VLSI Test Symposium (Cat. No.PR00146) Pub Date : 1999-04-26 DOI: 10.1109/VTEST.1999.766642

K. Chakrabarty, B. Murray, V. Iyengar

引用次数: 99

Partial scan using multi-hop state reachability analysis 部分扫描使用多跳状态可达性分析

Proceedings 17th IEEE VLSI Test Symposium (Cat. No.PR00146) Pub Date : 1999-04-26 DOI: 10.1109/VTEST.1999.766655

Sameer Sharma, M. Hsiao

引用次数: 6

An efficient BIST method for small buffers 小缓冲区的高效BIST方法

Proceedings 17th IEEE VLSI Test Symposium (Cat. No.PR00146) Pub Date : 1999-04-26 DOI: 10.1109/VTEST.1999.766672

W. Jone, D. Huang, S. S. Wu, Kuen-Jong Lee

引用次数: 22

Test generation for ground bounce in internal logic circuitry 内部逻辑电路接地反弹的测试生成

Proceedings 17th IEEE VLSI Test Symposium (Cat. No.PR00146) Pub Date : 1999-04-26 DOI: 10.1109/VTEST.1999.766652

Yi-Shing Chang, S. Gupta, M. Breuer

引用次数: 29