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Proceedings 17th IEEE VLSI Test Symposium (Cat. No.PR00146)最新文献

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Scan vector compression/decompression using statistical coding 扫描矢量压缩/解压使用统计编码
Proceedings 17th IEEE VLSI Test Symposium (Cat. No.PR00146) Pub Date : 1999-04-26 DOI: 10.1109/VTEST.1999.766654
A. Jas, Jayabrata Ghosh-Dastidar, N. Touba
{"title":"Scan vector compression/decompression using statistical coding","authors":"A. Jas, Jayabrata Ghosh-Dastidar, N. Touba","doi":"10.1109/VTEST.1999.766654","DOIUrl":"https://doi.org/10.1109/VTEST.1999.766654","url":null,"abstract":"A compression/decompression scheme based on statistical coding is presented for reducing the amount of test data that must be stored on a tester and transferred to each core in a core-based design. The test vectors provided by the core vendor are stored in compressed form in the tester memory and transferred to the chip where they are decompressed and applied to the core. Given the set of test vectors for a core, a statistical code is carefully selected so that it satisfies certain properties. These properties guarantee that it can be decoded by a simple pipelined decoder (placed at the serial input of the core's scan chain) which requires very small area. Results indicate that the proposed scheme can use a simple decoder to provide test data compression near that of an optimal Huffman code. The compression results in a two-fold advantage since both test storage and test time are reduced.","PeriodicalId":248104,"journal":{"name":"Proceedings 17th IEEE VLSI Test Symposium (Cat. No.PR00146)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1999-04-26","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131130537","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 267
Adaptive techniques for improving delay fault diagnosis 改进延迟故障诊断的自适应技术
Proceedings 17th IEEE VLSI Test Symposium (Cat. No.PR00146) Pub Date : 1999-04-26 DOI: 10.1109/VTEST.1999.766661
Jayabrata Ghosh-Dastidar, N. Touba
{"title":"Adaptive techniques for improving delay fault diagnosis","authors":"Jayabrata Ghosh-Dastidar, N. Touba","doi":"10.1109/VTEST.1999.766661","DOIUrl":"https://doi.org/10.1109/VTEST.1999.766661","url":null,"abstract":"This paper presents adaptive techniques for improving delay fault diagnosis. These techniques reduce the search space for direct probing which can save a lot of time during failure analysis. Given a set of two-pattern tests that resulted in faulty output responses, a procedure for deriving additional two-pattern tests that will improve the diagnostic resolution of delay faults is described. Two new techniques based on adjacency testing and delay-size bounding are presented. These techniques can be used to greatly reduce the number of suspect lines and thereby provide a more precise diagnosis that is valid for either single or multiple delay faults. Experimental results are shown indicating that the number of suspects can be reduced dramatically for both single and multiple delay faults.","PeriodicalId":248104,"journal":{"name":"Proceedings 17th IEEE VLSI Test Symposium (Cat. No.PR00146)","volume":"19 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1999-04-26","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133078717","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 38
Multiple design error diagnosis and correction in digital VLSI circuits 数字VLSI电路中的多重设计错误诊断与校正
Proceedings 17th IEEE VLSI Test Symposium (Cat. No.PR00146) Pub Date : 1999-04-26 DOI: 10.1109/VTEST.1999.766647
A. Veneris, I. Hajj, S. Venkataraman, W. Fuchs
{"title":"Multiple design error diagnosis and correction in digital VLSI circuits","authors":"A. Veneris, I. Hajj, S. Venkataraman, W. Fuchs","doi":"10.1109/VTEST.1999.766647","DOIUrl":"https://doi.org/10.1109/VTEST.1999.766647","url":null,"abstract":"With the increase in the complexity of VLSI circuit design, logic design errors can occur during synthesis. In this work, we present a method for multiple design error diagnosis and correction. Our approach uses the results of test vector simulation for both error detection and error correction. This makes it applicable to circuits with no global BDD representation. In addition, diagnosis is performed through an implicit enumeration of potentially erroneous lines in an effort to avoid the exponential explosion of the error space. Experimental results on ISCAS'85 benchmark circuits show that our approach can typically detect and correct 1, 2 and 3 errors within seconds of CPU time.","PeriodicalId":248104,"journal":{"name":"Proceedings 17th IEEE VLSI Test Symposium (Cat. No.PR00146)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1999-04-26","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131330888","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 19
Low-cost on-line test for digital filters 数字滤波器的低成本在线测试
Proceedings 17th IEEE VLSI Test Symposium (Cat. No.PR00146) Pub Date : 1999-04-26 DOI: 10.1109/VTEST.1999.766702
I. Bayraktaroglu, A. Orailoglu
{"title":"Low-cost on-line test for digital filters","authors":"I. Bayraktaroglu, A. Orailoglu","doi":"10.1109/VTEST.1999.766702","DOIUrl":"https://doi.org/10.1109/VTEST.1999.766702","url":null,"abstract":"A low-cost on-line test scheme for digital filters is proposed. The scheme uses an invariant of the digital filter, the frequency response at specific points, in order to detect possible malfunctioning of the circuit. The analysis performed indicates that 100% fault secureness is possible, if certain design constraints are followed.","PeriodicalId":248104,"journal":{"name":"Proceedings 17th IEEE VLSI Test Symposium (Cat. No.PR00146)","volume":"79 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1999-04-26","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131808527","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 8
Simulation-based design error diagnosis and correction in combinational digital circuits 基于仿真的组合数字电路设计错误诊断与校正
Proceedings 17th IEEE VLSI Test Symposium (Cat. No.PR00146) Pub Date : 1999-04-26 DOI: 10.1109/VTEST.1999.766649
D. Nayak, D. Walker
{"title":"Simulation-based design error diagnosis and correction in combinational digital circuits","authors":"D. Nayak, D. Walker","doi":"10.1109/VTEST.1999.766649","DOIUrl":"https://doi.org/10.1109/VTEST.1999.766649","url":null,"abstract":"This paper describes an approach to design error diagnosis and correction in combinational digital circuits. Our approach targets small errors introduced during the design process or due to specification changes. We incrementally use simulation to identify suspect nets, and then attempt correction based on our error model. We use multiple iterations to handle multiple errors. Experimental results on ISCAS'85 benchmarks are shown for circuits containing up to four random errors. Diagnosis and correction can be done quickly, with the bulk of the time going to diagnosis. Our tool is accurate in that even with multiple errors present, the corrected circuit is identical to the original most of the time.","PeriodicalId":248104,"journal":{"name":"Proceedings 17th IEEE VLSI Test Symposium (Cat. No.PR00146)","volume":"18 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1999-04-26","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"134412297","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 23
Implication and evaluation techniques for proving fault equivalence 故障等价证明的蕴涵与评价技术
Proceedings 17th IEEE VLSI Test Symposium (Cat. No.PR00146) Pub Date : 1999-04-26 DOI: 10.1109/VTEST.1999.766666
M. E. Amyeen, W. Fuchs, I. Pomeranz, V. Boppana
{"title":"Implication and evaluation techniques for proving fault equivalence","authors":"M. E. Amyeen, W. Fuchs, I. Pomeranz, V. Boppana","doi":"10.1109/VTEST.1999.766666","DOIUrl":"https://doi.org/10.1109/VTEST.1999.766666","url":null,"abstract":"Efficient identification of fault equivalence is essential for the completeness and efficiency of diagnostic test pattern generation. In this paper, we present new techniques to prove diagnostic fault equivalence. The techniques are based on implication of the faulty values, and functional evaluation at the dominator gate of the fault sites. The experimental results for all ISCAS85 circuits and full scan versions of ISCAS89 circuits show significant improvement compared to previously proposed techniques in both the number of equivalent pairs identified and the time to prove equivalence.","PeriodicalId":248104,"journal":{"name":"Proceedings 17th IEEE VLSI Test Symposium (Cat. No.PR00146)","volume":"14 9 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1999-04-26","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116777745","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 16
Verification of processor microarchitectures 处理器微架构的验证
Proceedings 17th IEEE VLSI Test Symposium (Cat. No.PR00146) Pub Date : 1999-04-26 DOI: 10.1109/VTEST.1999.766664
Jian Shen, J. Abraham
{"title":"Verification of processor microarchitectures","authors":"Jian Shen, J. Abraham","doi":"10.1109/VTEST.1999.766664","DOIUrl":"https://doi.org/10.1109/VTEST.1999.766664","url":null,"abstract":"This paper develops a new abstraction technique for processor microarchitecture validation. An abstract finite-state machine model is derived directly from the processor HDL description. This model, along with information about the instruction set, is used for validation coverage analysis. We also present automatic test generation algorithms for generating sequences for traversing state transition paths and covering snapshot and temporal events.","PeriodicalId":248104,"journal":{"name":"Proceedings 17th IEEE VLSI Test Symposium (Cat. No.PR00146)","volume":"74 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1999-04-26","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127365881","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 17
Advanced synchronous scan test methodology for multi clock domain ASICs 多时钟域asic先进同步扫描测试方法
Proceedings 17th IEEE VLSI Test Symposium (Cat. No.PR00146) Pub Date : 1999-04-26 DOI: 10.1109/VTEST.1999.766653
J. Schmid, Joachim Knäblein
{"title":"Advanced synchronous scan test methodology for multi clock domain ASICs","authors":"J. Schmid, Joachim Knäblein","doi":"10.1109/VTEST.1999.766653","DOIUrl":"https://doi.org/10.1109/VTEST.1999.766653","url":null,"abstract":"VLSI integrated circuits like complex ASICs and SOCs often require a multi clock design style for functional and/or performance reasons. Especially in telecom applications there are often many complex clock structures and clock domain transitions necessary. This requirement complicates the generation of structured test programs (Scan/ATPG, BIST) with current known methods. The result is a lot of test vectors which lead to long CPU and tester times for pattern generation, simulation and test application. Much effort is needed to generate skew insensitive test programs and verify them. This article describes a new approach of scan test implementation and generation of test programs for multi clock systems. By addition of a small and simple test circuit with standard library elements a almost push button solution is now possible. Effort for test program generation, CPU and tester time is reduced significantly. By use of a simple timeset, skew problems are eliminated since the circuit is fully synchronously tested by a two phase clocking scheme.","PeriodicalId":248104,"journal":{"name":"Proceedings 17th IEEE VLSI Test Symposium (Cat. No.PR00146)","volume":"352 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1999-04-26","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124453440","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 14
A new framework for automatic generation, insertion and verification of memory built-in self test units 一个用于自动生成、插入和验证内存内置自检单元的新框架
Proceedings 17th IEEE VLSI Test Symposium (Cat. No.PR00146) Pub Date : 1999-04-26 DOI: 10.1109/VTEST.1999.766694
K. Zarrineh, S. Upadhyaya
{"title":"A new framework for automatic generation, insertion and verification of memory built-in self test units","authors":"K. Zarrineh, S. Upadhyaya","doi":"10.1109/VTEST.1999.766694","DOIUrl":"https://doi.org/10.1109/VTEST.1999.766694","url":null,"abstract":"The design and architecture of a memory test synthesis framework for automatic generation, insertion and verification of memory BIST units is presented. We use a building block architecture which results in full customization of memory BIST units. The flexibility and efficiency of the framework are demonstrated by showing that memory BIST units with different architecture and characteristics could be generated, functionally verified and inserted in a short time. Custom memory test algorithms could be loaded in the supported programmable BIST unit and therefore any type of memory test algorithm could be realized.","PeriodicalId":248104,"journal":{"name":"Proceedings 17th IEEE VLSI Test Symposium (Cat. No.PR00146)","volume":"93 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1999-04-26","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114868758","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 7
Modular TSC checkers for Bose-Lin and Bose codes 用于Bose- lin和Bose代码的模块化TSC检查器
Proceedings 17th IEEE VLSI Test Symposium (Cat. No.PR00146) Pub Date : 1999-04-26 DOI: 10.1109/VTEST.1999.766689
X. Kavousianos, D. Nikolos
{"title":"Modular TSC checkers for Bose-Lin and Bose codes","authors":"X. Kavousianos, D. Nikolos","doi":"10.1109/VTEST.1999.766689","DOIUrl":"https://doi.org/10.1109/VTEST.1999.766689","url":null,"abstract":"It is well known that the most common errors in VLSI circuits are unidirectional in nature. Many applications need protection against up to t unidirectional errors, while some others against burst unidirectional errors. Bose-Lin codes are systematic t-unidirectional error detecting codes while Bose codes are burst unidirectional error detecting codes. In this paper we propose a modular method for designing double output checkers for Bose-Lin and Bose codes. The proposed checkers are Totally Self Checking (TSC) with respect to a realistic fault model including stuck-at, transistor stuck-open, transistor stuck-on, resistive bridging faults and breaks. The method is applicable to every code information length and the checkers are very compact and fast.","PeriodicalId":248104,"journal":{"name":"Proceedings 17th IEEE VLSI Test Symposium (Cat. No.PR00146)","volume":"7 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1999-04-26","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123821613","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 8
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