Advanced synchronous scan test methodology for multi clock domain ASICs

Abstract

VLSI integrated circuits like complex ASICs and SOCs often require a multi clock design style for functional and/or performance reasons. Especially in telecom applications there are often many complex clock structures and clock domain transitions necessary. This requirement complicates the generation of structured test programs (Scan/ATPG, BIST) with current known methods. The result is a lot of test vectors which lead to long CPU and tester times for pattern generation, simulation and test application. Much effort is needed to generate skew insensitive test programs and verify them. This article describes a new approach of scan test implementation and generation of test programs for multi clock systems. By addition of a small and simple test circuit with standard library elements a almost push button solution is now possible. Effort for test program generation, CPU and tester time is reduced significantly. By use of a simple timeset, skew problems are eliminated since the circuit is fully synchronously tested by a two phase clocking scheme.