Proceedings 17th IEEE VLSI Test Symposium (Cat. No.PR00146)最新文献_第4页

Efficient test generation for transient testing of analog circuits using partial numerical simulation 利用部分数值模拟有效生成模拟电路暂态测试

Proceedings 17th IEEE VLSI Test Symposium (Cat. No.PR00146) Pub Date : 1999-04-26 DOI: 10.1109/VTEST.1999.766668

P. Variyam, J. Hou, A. Chatterjee

{"title":"Efficient test generation for transient testing of analog circuits using partial numerical simulation","authors":"P. Variyam, J. Hou, A. Chatterjee","doi":"10.1109/VTEST.1999.766668","DOIUrl":"https://doi.org/10.1109/VTEST.1999.766668","url":null,"abstract":"Dynamic transient tests can give better parametric and catastrophic fault coverage than both static DC and frequency domain AC tests in minimum test time. However determination of optimum transient tests is a complex search problem. Previous researchers have used accurate but computationally expensive fault simulation to guide the search for the optimum transient tests. In this paper we propose to use partial numerical simulation to guide the search for the optimum input test stimulus. The proposed method dynamically adjusts the number of Newton Raphson iterations and transient simulation time steps to perform fast test generation without sacrificing the test quality (fault coverage). This heuristic relies on the observation that although partial numerical circuit simulation may be inaccurate for determining the exact faulty circuit response to an applied test stimulus, it can determine very well how one test stimulus performs relative to another in detecting a fault. Simulation studies show that test generation using partial numerical simulation can generate high quality tests much faster compared to test generation methods based on accurate simulation without compromising test quality.","PeriodicalId":248104,"journal":{"name":"Proceedings 17th IEEE VLSI Test Symposium (Cat. No.PR00146)","volume":"8 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1999-04-26","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115254064","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 15

Hierarchical test generation for analog circuits using incremental test development 使用增量测试开发的模拟电路分层测试生成

Proceedings 17th IEEE VLSI Test Symposium (Cat. No.PR00146) Pub Date : 1999-04-26 DOI: 10.1109/VTEST.1999.766679

R. Voorakaranam, A. Chatterjee

引用次数: 10

Analyzing the need for ATPG targeting GOS defects 分析了针对GOS缺陷的ATPG的需求

Proceedings 17th IEEE VLSI Test Symposium (Cat. No.PR00146) Pub Date : 1999-04-26 DOI: 10.1109/VTEST.1999.766698

E. Isern, M. Roca, J. Segura

引用次数: 1

Enhanced BIST-based diagnosis of FPGAs via boundary scan access 基于边界扫描的fpga增强bist诊断

Proceedings 17th IEEE VLSI Test Symposium (Cat. No.PR00146) Pub Date : 1999-04-26 DOI: 10.1109/VTEST.1999.766697

C. Hamilton, G. Gibson, S. Wijesuriya, C. Stroud

引用次数: 24

A new totally error propagating compactor for arbitrary cores with digital interfaces 基于数字接口的任意核全误差传播压缩器

Proceedings 17th IEEE VLSI Test Symposium (Cat. No.PR00146) Pub Date : 1999-04-26 DOI: 10.1109/VTEST.1999.766646

M. Gössel, A. Morosov, E. Sogomonyan

引用次数: 12

Error detecting refreshment for embedded DRAMs 嵌入式dram的错误检测刷新

Proceedings 17th IEEE VLSI Test Symposium (Cat. No.PR00146) Pub Date : 1999-04-26 DOI: 10.1109/VTEST.1999.766693

S. Hellebrand, H. Wunderlich, A. A. Ivaniuk, Y. Klimets, V. Yarmolik

引用次数: 20

From design-for-test to design-for-debug-and-test: analysis of requirements and limitations for 1149.1 从为测试而设计到为调试和测试而设计:1149.1的需求和限制分析

Proceedings 17th IEEE VLSI Test Symposium (Cat. No.PR00146) Pub Date : 1999-04-26 DOI: 10.1109/VTEST.1999.766706

G. Alves, J. Ferreira

引用次数: 17

Validation vector grade (VVG): a new coverage metric for validation and test 验证向量等级(VVG):用于验证和测试的新的覆盖度量

Proceedings 17th IEEE VLSI Test Symposium (Cat. No.PR00146) Pub Date : 1999-04-26 DOI: 10.1109/VTEST.1999.766663

Pradip A. Thaker, V. Agrawal, M. Zaghloul

{"title":"Validation vector grade (VVG): a new coverage metric for validation and test","authors":"Pradip A. Thaker, V. Agrawal, M. Zaghloul","doi":"10.1109/VTEST.1999.766663","DOIUrl":"https://doi.org/10.1109/VTEST.1999.766663","url":null,"abstract":"Current code coverage metrics used in high level VLSI design methodology are based on statement, branch, toggle and condition coverages of the HDL code obtained by simulating validation vectors. These measures allow the designer to find sections of the HDL code not executed during validation. Feedback from the code coverage analysis helps generate additional vectors to exercise previously unexercised functionality. In this paper, we explore the relationship between results of RTL code coverage and the gate level fault coverage. Based on the observations of this empirical study we propose a new and improved code coverage metric \"Validation Vector Grade (VVG)\". The VVG-approach modifies code coverage metrics by adding the concepts of observability and arithmetic fault library. VVG is an improved validation metric, which can also be used for early testability analysis at the RT level. Results of the VVG-approach at RT level are shown to be good indicators of the structural fault coverage. Experiments on actual telecommunication VLSI chip designs show that the VVG reported at the RT level can predict the post-synthesis gate level fault coverage with an error margin less than 4%. Also, the improvements in VVG at the RT level due to high-level design changes or added vectors track improvements in gate level fault coverage.","PeriodicalId":248104,"journal":{"name":"Proceedings 17th IEEE VLSI Test Symposium (Cat. No.PR00146)","volume":"40 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1999-04-26","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129168541","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 40

A fault simulation based test pattern generator for synchronous sequential circuits 基于故障仿真的同步时序电路测试图发生器

Proceedings 17th IEEE VLSI Test Symposium (Cat. No.PR00146) Pub Date : 1999-04-26 DOI: 10.1109/VTEST.1999.766674

Ruifeng Guo, I. Pomeranz, S. Reddy

引用次数: 20

Programmable embedded self-testing checkers for all-unidirectional error-detecting codes 全单向错误检测代码的可编程嵌入式自检检查器

Proceedings 17th IEEE VLSI Test Symposium (Cat. No.PR00146) Pub Date : 1999-04-26 DOI: 10.1109/VTEST.1999.766690

A. P. Stroele, S. Tarnick

引用次数: 12