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Proceedings 17th IEEE VLSI Test Symposium (Cat. No.PR00146)最新文献

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Using temporal constraints for eliminating crosstalk candidates for design and test 利用时间约束来消除设计和测试中的串扰候选者
Proceedings 17th IEEE VLSI Test Symposium (Cat. No.PR00146) Pub Date : 1999-04-26 DOI: 10.1109/VTEST.1999.766650
Michael A. Margolese, F. Ferguson
{"title":"Using temporal constraints for eliminating crosstalk candidates for design and test","authors":"Michael A. Margolese, F. Ferguson","doi":"10.1109/VTEST.1999.766650","DOIUrl":"https://doi.org/10.1109/VTEST.1999.766650","url":null,"abstract":"This paper describes a simple algorithm for eliminating possible aggressor-victim net pairs for crosstalk analysis. This algorithm makes use of the observation that timing constraints in sequential circuits apply to crosstalk induced pulses. We show how this algorithm can be applied to a design to prune the candidate list for ATPG to detect crosstalk glitches that are introduced by manufacturing defects.","PeriodicalId":248104,"journal":{"name":"Proceedings 17th IEEE VLSI Test Symposium (Cat. No.PR00146)","volume":"62 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1999-04-26","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116979179","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 9
Delay fault testing of designs with embedded IP cores 嵌入式IP核设计的延迟故障测试
Proceedings 17th IEEE VLSI Test Symposium (Cat. No.PR00146) Pub Date : 1999-04-26 DOI: 10.1109/VTEST.1999.766660
HyungWon Kim, J. Hayes
{"title":"Delay fault testing of designs with embedded IP cores","authors":"HyungWon Kim, J. Hayes","doi":"10.1109/VTEST.1999.766660","DOIUrl":"https://doi.org/10.1109/VTEST.1999.766660","url":null,"abstract":"Conventional methods cannot effectively verify path delays of designs employing IP circuits (cores) whose implementation details are hidden. A delay fault ATPG method for such designs is proposed that employs a scan technique called selectively transparent scan (STS). Experimental results are presented which show that the STS method can robustly test paths of a specified delay range in core-based circuits, and substantially reduce test length.","PeriodicalId":248104,"journal":{"name":"Proceedings 17th IEEE VLSI Test Symposium (Cat. No.PR00146)","volume":"35 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1999-04-26","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130553561","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 6
A novel test methodology for MEMS magnetic micromotors 一种新的MEMS磁性微电机测试方法
Proceedings 17th IEEE VLSI Test Symposium (Cat. No.PR00146) Pub Date : 1999-04-26 DOI: 10.1109/VTEST.1999.766677
Bruce C. Kim, Krishnaveni Marella
{"title":"A novel test methodology for MEMS magnetic micromotors","authors":"Bruce C. Kim, Krishnaveni Marella","doi":"10.1109/VTEST.1999.766677","DOIUrl":"https://doi.org/10.1109/VTEST.1999.766677","url":null,"abstract":"This paper describes a novel test methodology for testing MEMS magnetic micromotor. A fault simulation model has been developed for the micromotor. The test apparatus consists of a low frequency sinusoidal source and a resonator that is tuned to the normal operating frequency of the micromotor. The test method described in this paper is used to detect complete open and near-open defects in the stator coils of the micromotor.","PeriodicalId":248104,"journal":{"name":"Proceedings 17th IEEE VLSI Test Symposium (Cat. No.PR00146)","volume":"28 6 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1999-04-26","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133650238","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 5
A current integrator for BIST of mixed-signal ICs 一种用于混合信号集成电路的电流积分器
Proceedings 17th IEEE VLSI Test Symposium (Cat. No.PR00146) Pub Date : 1999-04-26 DOI: 10.1109/VTEST.1999.766681
S. Tabatabaei, A. Ivanov
{"title":"A current integrator for BIST of mixed-signal ICs","authors":"S. Tabatabaei, A. Ivanov","doi":"10.1109/VTEST.1999.766681","DOIUrl":"https://doi.org/10.1109/VTEST.1999.766681","url":null,"abstract":"A novel built-in current integrator (BICI) is proposed for measuring the average supply current (I/sub DD/) of embedded circuit blocks. Such a circuit can be used both as a current signature generator and power monitor. The BICI uses only small capacitors (total 72 pF), a simple comparator, 7 switches, and a counter to perform integration over a long time (1 ms) window and digitize I/sub DD/. The BICI generates a digital signature proportional to I/sub DD/ and occupies a small area which make it suitable for BIST applications on mixed-signal ICs. The circuit has been implemented using a standard 0.5 /spl mu/ CMOS technology. Circuit performance trade-offs are analyzed and optimization guidelines provided. Simulation results are also included.","PeriodicalId":248104,"journal":{"name":"Proceedings 17th IEEE VLSI Test Symposium (Cat. No.PR00146)","volume":"55 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1999-04-26","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130853899","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 2
Extending the pseudo-stuck-at fault model to provide complete IDDQ coverage 扩展伪卡在故障模型以提供完整的IDDQ覆盖
Proceedings 17th IEEE VLSI Test Symposium (Cat. No.PR00146) Pub Date : 1999-04-26 DOI: 10.1109/VTEST.1999.766656
R. Aitken
{"title":"Extending the pseudo-stuck-at fault model to provide complete IDDQ coverage","authors":"R. Aitken","doi":"10.1109/VTEST.1999.766656","DOIUrl":"https://doi.org/10.1109/VTEST.1999.766656","url":null,"abstract":"Since its inception, the pseudo-stuck-at fault model has demonstrated its usefulness in generating IDDQ patterns, calculating coverage, and diagnosing defects. However, the model's definition has lacked rigor, which has resulted in multiple, incompatible, interpretations. This paper provides a complete definition for the model and demonstrates how variations will cause a loss of defect coverage. The covering relationship between the pseudo-stuck-at (PSA) model and leakage faults is proven for all combinational CMOS cells. This relationship is extended to show the effect that undetectable PSA faults have on leakage fault coverage. It is shown how to apply the model to sequential cells such as flip-flops and latches. The PSA model is also extended to cover both short and open faults in chip interconnect. A weighting function is introduced to tie the coverage more closely to process defect statistics. Finally, experimental results are given to show the effectiveness of the model on actual ASICs.","PeriodicalId":248104,"journal":{"name":"Proceedings 17th IEEE VLSI Test Symposium (Cat. No.PR00146)","volume":"62 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1999-04-26","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114566366","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 10
An effective BIST architecture for sequential fault testing in array multipliers 阵列乘法器序列故障测试的有效BIST结构
Proceedings 17th IEEE VLSI Test Symposium (Cat. No.PR00146) Pub Date : 1999-04-26 DOI: 10.1109/VTEST.1999.766673
M. Psarakis, A. Paschalis, D. Gizopoulos, Y. Zorian
{"title":"An effective BIST architecture for sequential fault testing in array multipliers","authors":"M. Psarakis, A. Paschalis, D. Gizopoulos, Y. Zorian","doi":"10.1109/VTEST.1999.766673","DOIUrl":"https://doi.org/10.1109/VTEST.1999.766673","url":null,"abstract":"Sequential fault testing approaches for array multipliers proposed in the past target only external testing and impose significant hardware overhead due to excessive DFT modifications. In this paper we present, for the first time, a BIST architecture which does not require any DFT modifications in the multiplier structure and provides a fault coverage larger than 99% for a comprehensive sequential fault model (RS-CFM) for any multiplier size. Both robust and non-robust testing are considered. The applicability of the BIST architecture is further justified considering the case of the transistor stuck-open fault model, where a fault coverage larger than 99% is also achieved in any case.","PeriodicalId":248104,"journal":{"name":"Proceedings 17th IEEE VLSI Test Symposium (Cat. No.PR00146)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1999-04-26","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124392638","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 5
The limits of digital testing for dynamic circuits 动态电路数字测试的局限性
Proceedings 17th IEEE VLSI Test Symposium (Cat. No.PR00146) Pub Date : 1999-04-26 DOI: 10.1109/VTEST.1999.766643
R. Adams, E. S. Cooley
{"title":"The limits of digital testing for dynamic circuits","authors":"R. Adams, E. S. Cooley","doi":"10.1109/VTEST.1999.766643","DOIUrl":"https://doi.org/10.1109/VTEST.1999.766643","url":null,"abstract":"Dynamic circuits are faster and have a different circuit topology from their static counterparts. These topological differences require changes in fault modeling and test strategies. Digital testing, while adequate far static logic, misses numerous faults in dynamic circuits due to the implicit assumptions surrounding the stuck-at fault model. A fault model reduction technique was employed which simplifies large circuits without loss of information on the ways that circuits can fail. Numerous faults were singly inserted and possible faulty operation was analyzed. The faults missed by digital testing are detailed and alternative test strategies are discussed. In many cases significant dynamic circuit robustness is lost due to faults which are digitally undetectable.","PeriodicalId":248104,"journal":{"name":"Proceedings 17th IEEE VLSI Test Symposium (Cat. No.PR00146)","volume":"8 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1999-04-26","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125623245","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 3
A new method for diagnosing multiple stuck-at faults using multiple and single fault simulations 基于多故障和单故障仿真的多卡滞故障诊断新方法
Proceedings 17th IEEE VLSI Test Symposium (Cat. No.PR00146) Pub Date : 1999-04-26 DOI: 10.1109/VTEST.1999.766648
Hiroshi Takahashi, K. Boateng, Y. Takamatsu
{"title":"A new method for diagnosing multiple stuck-at faults using multiple and single fault simulations","authors":"Hiroshi Takahashi, K. Boateng, Y. Takamatsu","doi":"10.1109/VTEST.1999.766648","DOIUrl":"https://doi.org/10.1109/VTEST.1999.766648","url":null,"abstract":"In this paper, we propose a new method that uses single and multiple fault simulations to diagnose multiple stuck-at faults in combinational circuits. On the assumption that all suspected faults are equally likely in the faulty circuit, multiple fault simulations are performed. Depending on whether or not a multiple fault simulation results in primary output values that agree with the observed values, faults are added to or removed from a set of suspected faults. Faults which are to be added to or removed from the set of suspected faults are determined using single fault simulation. Diagnosis is effected by repeated additions and removals of faults. The effectiveness of the method of diagnosis has been evaluated by experiments conducted on benchmark circuits. The proposed method achieves a small number of suspected faults by simple processing. Thus, the method will be useful as a preprocessing stage of diagnosis using the electron-beam tester.","PeriodicalId":248104,"journal":{"name":"Proceedings 17th IEEE VLSI Test Symposium (Cat. No.PR00146)","volume":"19 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1999-04-26","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115401804","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 13
Defect-oriented test scheduling 面向缺陷的测试调度
Proceedings 17th IEEE VLSI Test Symposium (Cat. No.PR00146) Pub Date : 1999-04-26 DOI: 10.1109/VTEST.1999.766700
Wanli Jiang, B. Vinnakota
{"title":"Defect-oriented test scheduling","authors":"Wanli Jiang, B. Vinnakota","doi":"10.1109/VTEST.1999.766700","DOIUrl":"https://doi.org/10.1109/VTEST.1999.766700","url":null,"abstract":"Test time can be reduced by ordering tests so as to fail defective units early in the test process. An ordering algorithm requires information on the ability of tests to detect defective units. We obtain it by applying all possible tests to a small subset of manufactured units and assume the information obtained from this sub-set is representative. We develop a simple polynomial-time heuristic which uses the information from the sample set to order tests. The heuristic, based on criteria that offer local optimality, offers globally optimal solutions in many cases. Optimal test ordering algorithms require execution time which is exponential in the number of tests applied. In our experiments, the heuristic results in a significant reduction in test time for manufactured digital and analog ICs.","PeriodicalId":248104,"journal":{"name":"Proceedings 17th IEEE VLSI Test Symposium (Cat. No.PR00146)","volume":"3 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1999-04-26","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115426375","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 75
Comparative study of CA-based PRPGs and LFSRs with phase shifters 基于ca的prpg与带移相器的lfsr的比较研究
Proceedings 17th IEEE VLSI Test Symposium (Cat. No.PR00146) Pub Date : 1999-04-26 DOI: 10.1109/VTEST.1999.766671
J. Rajski, Grzegorz Mrugalski, J. Tyszer
{"title":"Comparative study of CA-based PRPGs and LFSRs with phase shifters","authors":"J. Rajski, Grzegorz Mrugalski, J. Tyszer","doi":"10.1109/VTEST.1999.766671","DOIUrl":"https://doi.org/10.1109/VTEST.1999.766671","url":null,"abstract":"The paper presents a comparative study of randomness properties of patterns generated by one-dimensional linear hybrid cellular automata (LHCA) and linear feedback shift registers (LFSRs) with phase shifters on their outputs. It is shown that properly synthesized phase shifters allow LFSRs to match performance of the LHCAs as pseudo-random pattern generators (PRPGs), in marked contrast to several suggestions that LHCAs can outperform LFSRs in variety of testing applications.","PeriodicalId":248104,"journal":{"name":"Proceedings 17th IEEE VLSI Test Symposium (Cat. No.PR00146)","volume":"21 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1999-04-26","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126587455","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 23
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