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Proceedings 17th IEEE VLSI Test Symposium (Cat. No.PR00146)最新文献

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Preliminary Outline of the IEEE PI 500 Scalable Architecture for Testing Embedded Cores 用于测试嵌入式核的IEEE PI 500可扩展架构的初步大纲
Proceedings 17th IEEE VLSI Test Symposium (Cat. No.PR00146) Pub Date : 1999-04-25 DOI: 10.1109/VTEST.1999.766707
S. Adham, D. Burek, C. J. Clark, M. Collins, G. Giles, A. Sales, E. Marinissen, T. McLaurin, J. Monzel, F. Muradali, J. Rajoki, R. Rajsuman, M. Ricchatti, D. Stannard, J. Udell, P. Varma, L. Whetsel, A. Zamfirescu, Y. Zorian
{"title":"Preliminary Outline of the IEEE PI 500 Scalable Architecture for Testing Embedded Cores","authors":"S. Adham, D. Burek, C. J. Clark, M. Collins, G. Giles, A. Sales, E. Marinissen, T. McLaurin, J. Monzel, F. Muradali, J. Rajoki, R. Rajsuman, M. Ricchatti, D. Stannard, J. Udell, P. Varma, L. Whetsel, A. Zamfirescu, Y. Zorian","doi":"10.1109/VTEST.1999.766707","DOIUrl":"https://doi.org/10.1109/VTEST.1999.766707","url":null,"abstract":"This paper provides an outline of the proposals of the IEEE P1500 Scalable Architecture Task Force and defines what is in the scope of the Task Force’s current standardization activity. The overall architecture of the proposed standard is described, followed by several sections in which further details are provided with respect to relevant sub-domains of the architecture. Note that this paper is only a preliminary overview of the current direction of the Task Force, and by far not a full draft standard.","PeriodicalId":248104,"journal":{"name":"Proceedings 17th IEEE VLSI Test Symposium (Cat. No.PR00146)","volume":"42 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1999-04-25","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125578794","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 10
REDO-random excitation and deterministic observation-first commercial experiment 随机激励与确定性观测先行商业实验
Proceedings 17th IEEE VLSI Test Symposium (Cat. No.PR00146) Pub Date : 1999-04-25 DOI: 10.1109/VTEST.1999.766675
M. Grimaila, Sooryong Lee, Jennifer Dworak, K. Butler, Bret A. Stewart, H. Balachandran, B. Houchins, Vineet Mathur, Jaehong Park, Li-C. Wang, M. R. Mercer
{"title":"REDO-random excitation and deterministic observation-first commercial experiment","authors":"M. Grimaila, Sooryong Lee, Jennifer Dworak, K. Butler, Bret A. Stewart, H. Balachandran, B. Houchins, Vineet Mathur, Jaehong Park, Li-C. Wang, M. R. Mercer","doi":"10.1109/VTEST.1999.766675","DOIUrl":"https://doi.org/10.1109/VTEST.1999.766675","url":null,"abstract":"For many years, non-target detection experiments have been simulated by using AND/OR bridges or gross delay faults as surrogates. For example, the defective part level can be estimated based upon surrogate detection when test patterns target stuck-at faults in the circuit. For the first time, test pattern generation techniques that attempt to maximize non-target defect detection have been used to test a real, 100% scanned, commercial chip consisting of 75 K logic gates. In this experiment, the defective part level for REDO-based patterns was 1,288 parts per million lower than that achieved by DC stuck-at based patterns generated using today's state of the art tools and techniques.","PeriodicalId":248104,"journal":{"name":"Proceedings 17th IEEE VLSI Test Symposium (Cat. No.PR00146)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1999-04-25","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128692134","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 126
New procedures for identifying undetectable and redundant faults in synchronous sequential circuits 识别同步顺序电路中不可检测和冗余故障的新程序
Proceedings 17th IEEE VLSI Test Symposium (Cat. No.PR00146) Pub Date : 1999-04-25 DOI: 10.1109/VTEST.1999.766676
S. Reddy, I. Pomeranz, N. Z. Basturkmen, X. Lin
{"title":"New procedures for identifying undetectable and redundant faults in synchronous sequential circuits","authors":"S. Reddy, I. Pomeranz, N. Z. Basturkmen, X. Lin","doi":"10.1109/VTEST.1999.766676","DOIUrl":"https://doi.org/10.1109/VTEST.1999.766676","url":null,"abstract":"We present three new procedures for identifying undetectable and redundant faults in synchronous sequential circuits. The procedures use an iterative logic array of limited length, into which faults are injected in different ways. The proposed procedures help identify undetectable and redundant faults that cannot be identified by existing procedures based on iterative logic arrays of limited length.","PeriodicalId":248104,"journal":{"name":"Proceedings 17th IEEE VLSI Test Symposium (Cat. No.PR00146)","volume":"19 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1999-04-25","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123070570","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 17
Design technology research and education for deep-submicron systems of the next century 下个世纪深亚微米系统的设计技术研究和教育
Proceedings 17th IEEE VLSI Test Symposium (Cat. No.PR00146) Pub Date : 1900-01-01 DOI: 10.1109/VTEST.1999.766639
H. de Man
{"title":"Design technology research and education for deep-submicron systems of the next century","authors":"H. de Man","doi":"10.1109/VTEST.1999.766639","DOIUrl":"https://doi.org/10.1109/VTEST.1999.766639","url":null,"abstract":"Deep-submicron technology combined with the tremendous growth of global networking leads to SoC and requires a rethinking of communication architectures and disciplinary design methodologies. This creates the need for SoC engineers to be able to bridge the gap between system level concepts and their implementation in heterogeneous silicon architectures. The concept of a design center is introduced where academic staff and students team-up around visionary information technology design projects. Building actual software-hardware prototype demonstrators is undertaken as a means to create new methodologies that give rise to new CAE tools, libraries, teaching material and training courses available over the network. A design center is the ideal environment for educating the SoC engineer. In such schools emphasis is on broad education in the basics of computing, communications and components. Design practice (including non-technical skills) are learned by team-based integrated projects in product design.","PeriodicalId":248104,"journal":{"name":"Proceedings 17th IEEE VLSI Test Symposium (Cat. No.PR00146)","volume":"34 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1900-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115517290","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
On the comparison of /spl Delta/I/sub DDQ/ and I/sub DDQ/ testing /spl Delta/I/sub DDQ/与I/sub DDQ/测试的比较
Proceedings 17th IEEE VLSI Test Symposium (Cat. No.PR00146) Pub Date : 1900-01-01 DOI: 10.1109/VTEST.1999.766658
C. Thibeault
{"title":"On the comparison of /spl Delta/I/sub DDQ/ and I/sub DDQ/ testing","authors":"C. Thibeault","doi":"10.1109/VTEST.1999.766658","DOIUrl":"https://doi.org/10.1109/VTEST.1999.766658","url":null,"abstract":"The purpose of this paper is to compare differential Iddq to Iddq itself; in their capabilities of detecting active current defects/faults, as bridging faults. To perform this comparison, a mathematical framework is developed, based on assumptions validated with data from the Sematech experiment S121. The comparison results reveal that the probability of false test decision can be reduced by orders of magnitude by using differential Iddq instead of Iddq. Based on the same framework, we also show that a wise vector selection may contribute to decrease by orders of magnitude the probability of a false test decision. Finally, we investigate the applicability of differential Iddq with deep-submicron technologies, by estimating the number of (pairs of) vectors required to achieve a given test qualify level. The proposed framework and the results help to understand the tendencies and to identify the requirements in order to meet the challenges of deep-submicron current testing.","PeriodicalId":248104,"journal":{"name":"Proceedings 17th IEEE VLSI Test Symposium (Cat. No.PR00146)","volume":"39 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1900-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121760025","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 42
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