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2018 International Semiconductor Conference (CAS)最新文献

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Fault Impact Assessment for Automotive Smart Power Products in an Electric Power Steering Application 汽车智能电源产品在电动助力转向应用中的故障影响评估
2018 International Semiconductor Conference (CAS) Pub Date : 2018-10-01 DOI: 10.1109/SMICND.2018.8539772
Jonas Stricker, C. Kain, Andi Buzo, Jérôme Kirscher, L. Maurer, G. Pelz
{"title":"Fault Impact Assessment for Automotive Smart Power Products in an Electric Power Steering Application","authors":"Jonas Stricker, C. Kain, Andi Buzo, Jérôme Kirscher, L. Maurer, G. Pelz","doi":"10.1109/SMICND.2018.8539772","DOIUrl":"https://doi.org/10.1109/SMICND.2018.8539772","url":null,"abstract":"The paper presents a methodology to propagate the consequences of random hardware faults in automotive smart power products to the application level. To accomplish this, the random hardware faults on chip level are assessed through fault injection into circuit simulations and are collapsed to come up with the relevant fault modes of a certain chip block. Then, these fault modes are propagated to the application level by injecting them into application simulations. The above is accomplished in an automated, seamless flow, which supports the engineering judgment in safety analysis by simulation results. The viability of the proposed approach is shown along a real-life example application (electric power steering) and a related smart power function (current measurement in the three phases). 1","PeriodicalId":247062,"journal":{"name":"2018 International Semiconductor Conference (CAS)","volume":"67 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2018-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124538956","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
From Pentacene Thin Film Transistor to Nanostructured Materials Synthesis for Green Organic-TFT 从五苯薄膜晶体管到绿色有机tft纳米结构材料的合成
2018 International Semiconductor Conference (CAS) Pub Date : 2018-10-01 DOI: 10.1109/SMICND.2018.8539760
C. Ravariu, Dan Eduard Mihalcscu, D. Istrati, M. Stanca
{"title":"From Pentacene Thin Film Transistor to Nanostructured Materials Synthesis for Green Organic-TFT","authors":"C. Ravariu, Dan Eduard Mihalcscu, D. Istrati, M. Stanca","doi":"10.1109/SMICND.2018.8539760","DOIUrl":"https://doi.org/10.1109/SMICND.2018.8539760","url":null,"abstract":"As first aim, a start Pentacene-Organic Thin Film Transistor - OTFT - is simulated to capture the static characteristics and to find the matching parameters with the experimental set-up. The current vectors validate the main conduction way and the OTFT functionality. In a second stage, the basic technology of an alternative polymer grafted on nanomaterial synthesis, is depicted. The Fe304 core-shell nanoparticles are assembled by an external shell of paraaminobenzoic acid (PABA). The final scope will be OTFT construction by these green technologies. The first step: the Fe3O4/PAbathin films synthesis and characterization, is successfully performed.","PeriodicalId":247062,"journal":{"name":"2018 International Semiconductor Conference (CAS)","volume":"92 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2018-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"134316474","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 4
Multi-Scale Finite Element Modeling of CNT-Polymer-Composites 碳纳米管-聚合物-复合材料的多尺度有限元建模
2018 International Semiconductor Conference (CAS) Pub Date : 2018-10-01 DOI: 10.1109/SMICND.2018.8539799
Michael Schiebold, J. Mehner
{"title":"Multi-Scale Finite Element Modeling of CNT-Polymer-Composites","authors":"Michael Schiebold, J. Mehner","doi":"10.1109/SMICND.2018.8539799","DOIUrl":"https://doi.org/10.1109/SMICND.2018.8539799","url":null,"abstract":"A hierarchical multi-scale approach is used to model a composite consisting of carbon nanotubes and a polymer which can be used as pressure sensor matrix to prevent people from decubitus ulcer. Starting with the modeling of a carbon nanotube and the calculation of its equivalent cylinder properties. Subsequently the cylinders which replace the CNTs are randomly distributed in the polymer such that homogenization techniques leading to the mechanical properties of the composite.","PeriodicalId":247062,"journal":{"name":"2018 International Semiconductor Conference (CAS)","volume":"12 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2018-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129547744","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 2
High Pillar Doping Concentration for SiC Superjunction IGBTs SiC超结igbt的高柱掺杂浓度
2018 International Semiconductor Conference (CAS) Pub Date : 2018-10-01 DOI: 10.1109/SMICND.2018.8539824
H. Kang, F. Udrea
{"title":"High Pillar Doping Concentration for SiC Superjunction IGBTs","authors":"H. Kang, F. Udrea","doi":"10.1109/SMICND.2018.8539824","DOIUrl":"https://doi.org/10.1109/SMICND.2018.8539824","url":null,"abstract":"This paper is a theoretical study of the optimum doping concentration for the n and p pillars of a superjunction IGBT. As the concentration of the pillar for a silicon-carbide superjunction device increases up to 10 times higher than that of silicon, unipolar drift current in each pillar can be predominant over the bipolar action. The increased doping concentration effectively reduces the potential drop in the pillar for the on-state conduction.","PeriodicalId":247062,"journal":{"name":"2018 International Semiconductor Conference (CAS)","volume":"173 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2018-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116605028","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
Integrated Circuits 3 Student Papers 集成电路3学生论文
2018 International Semiconductor Conference (CAS) Pub Date : 2018-10-01 DOI: 10.1109/smicnd.2018.8539838
{"title":"Integrated Circuits 3 Student Papers","authors":"","doi":"10.1109/smicnd.2018.8539838","DOIUrl":"https://doi.org/10.1109/smicnd.2018.8539838","url":null,"abstract":"Integrated Circuits 3 Student papers","PeriodicalId":247062,"journal":{"name":"2018 International Semiconductor Conference (CAS)","volume":"136 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2018-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115903361","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Wide Dynamic Range Current Mirror 宽动态范围电流反射镜
2018 International Semiconductor Conference (CAS) Pub Date : 2018-10-01 DOI: 10.1109/SMICND.2018.8539765
A. Cracan, G. Bonteanu
{"title":"Wide Dynamic Range Current Mirror","authors":"A. Cracan, G. Bonteanu","doi":"10.1109/SMICND.2018.8539765","DOIUrl":"https://doi.org/10.1109/SMICND.2018.8539765","url":null,"abstract":"A novel circuit solution for implementing a known low-voltage current mirror topology is presented. It demonstrates a close to the rail input and output voltages (one saturation voltage at the input and two saturation voltages at the output) while being able to support an input current variation of orders of magnitude. The structure uses dynamic biasing in order to keep the transistors in the active region.","PeriodicalId":247062,"journal":{"name":"2018 International Semiconductor Conference (CAS)","volume":"468 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2018-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121463618","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 2
Nanoscience; Micro and Nanophotonics (Poster Session) 纳米科学;微纳米光子学(海报部分)
2018 International Semiconductor Conference (CAS) Pub Date : 2018-10-01 DOI: 10.1109/smicnd.2018.8539436
{"title":"Nanoscience; Micro and Nanophotonics (Poster Session)","authors":"","doi":"10.1109/smicnd.2018.8539436","DOIUrl":"https://doi.org/10.1109/smicnd.2018.8539436","url":null,"abstract":"Nanoscience; Micro and Nanophotonics (Poster session)","PeriodicalId":247062,"journal":{"name":"2018 International Semiconductor Conference (CAS)","volume":"94 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2018-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125803889","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Numerical Simulations of Radiation Damage Effects in Active-Edge Silicon Pixel Sensors for High-Energy Physics Experiments 高能物理实验有源边缘硅像素传感器辐射损伤效应的数值模拟
2018 International Semiconductor Conference (CAS) Pub Date : 2018-10-01 DOI: 10.1109/SMICND.2018.8539752
D. Djamai, E. Gkougkousis, M. Chahdi, A. Lounis, S. Oussalah
{"title":"Numerical Simulations of Radiation Damage Effects in Active-Edge Silicon Pixel Sensors for High-Energy Physics Experiments","authors":"D. Djamai, E. Gkougkousis, M. Chahdi, A. Lounis, S. Oussalah","doi":"10.1109/SMICND.2018.8539752","DOIUrl":"https://doi.org/10.1109/SMICND.2018.8539752","url":null,"abstract":"High-energy physics experiments at the future CERN High Luminosity LHC (Large Hadron Collider) require highly segmented pixelated sensors of increased geometrical efficiency and the ability of withstanding extremely high radiation damage. The performance of planar n-on-p sensors with active edges is simulated at very high fluences (2×1016neq/cm2), using a recent three level trap model for p-type silicon material. Precise structural definition is achieved by investigating the doping profile of the devices via the Secondary Ion Mass Spectrometry technique. The breakdown voltage, and hole density distribution are studied as a function of radiation fluences.","PeriodicalId":247062,"journal":{"name":"2018 International Semiconductor Conference (CAS)","volume":"26 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2018-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126139554","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Over-Temperature Protection for a Switched-Capacitor DC-DC Converter with Controlled Charging Current 控制充电电流的开关电容DC-DC变换器的过温保护
2018 International Semiconductor Conference (CAS) Pub Date : 2018-10-01 DOI: 10.1109/SMICND.2018.8539822
C. Pleşa, M. Neag, C. Boianceanu
{"title":"Over-Temperature Protection for a Switched-Capacitor DC-DC Converter with Controlled Charging Current","authors":"C. Pleşa, M. Neag, C. Boianceanu","doi":"10.1109/SMICND.2018.8539822","DOIUrl":"https://doi.org/10.1109/SMICND.2018.8539822","url":null,"abstract":"This paper presents an over-temperature protection (OTP) circuit for a DC-DC converter based on switching capacitors (SC DC-DC). The circuit was designed by using a two-step approach that encompasses running both electrical and electro-thermal simulations. The die temperature distribution was analyzed for two critical operational scenarios in order to identify the worst case and to provide design data for implementing a robust and precise OTP. Finally, a design example of a SC DC-DC with OTP is presented in some detail, complete with the key electrical and electro-thermal simulation results.","PeriodicalId":247062,"journal":{"name":"2018 International Semiconductor Conference (CAS)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2018-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128977347","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
A High Performance Mixed-Voltage Digital Output Buffer 一种高性能混合电压数字输出缓冲器
2018 International Semiconductor Conference (CAS) Pub Date : 2018-10-01 DOI: 10.1109/SMICND.2018.8539840
A. Dragan, Andrei Enache, A. Negut, A. Tache, G. Brezeanu
{"title":"A High Performance Mixed-Voltage Digital Output Buffer","authors":"A. Dragan, Andrei Enache, A. Negut, A. Tache, G. Brezeanu","doi":"10.1109/SMICND.2018.8539840","DOIUrl":"https://doi.org/10.1109/SMICND.2018.8539840","url":null,"abstract":"A digital push-pull output buffer is designed and implemented in a 0.18μm CMOS EEPROM process. The buffer acts as an interface between an internal low voltage and an external, higher level voltage. The circuit can operate in a wide range of power supply voltages, from 1.6V to 5.6V, at data rates of up to 20 Mbps. These performances were achieved through topology changes to a classic digital buffer.","PeriodicalId":247062,"journal":{"name":"2018 International Semiconductor Conference (CAS)","volume":"178 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2018-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125390965","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 2
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