2009 International Symposium on VLSI Design, Automation and Test最新文献_第5页

Software-enabled design visibility enhancement for failure analysis process improvement 软件支持的设计可见性增强，用于故障分析过程改进

2009 International Symposium on VLSI Design, Automation and Test Pub Date : 2009-04-28 DOI: 10.1109/VDAT.2009.5158126

Chia-Chih Yen, Shen-Tien Lin, Kai Yang, Jerome Peillat, Paul Gibson, E. Auvray

引用次数: 2

Virtual prototyping increases productivity - A case study 虚拟原型提高生产力-一个案例研究

2009 International Symposium on VLSI Design, Automation and Test Pub Date : 2009-04-28 DOI: 10.1109/VDAT.2009.5158104

Prasad Avss, Sasidharan Prasant, R. Jain

{"title":"Virtual prototyping increases productivity - A case study","authors":"Prasad Avss, Sasidharan Prasant, R. Jain","doi":"10.1109/VDAT.2009.5158104","DOIUrl":"https://doi.org/10.1109/VDAT.2009.5158104","url":null,"abstract":"With the advancement in technology, more and more functionality is being integrated into SoCs. A typical SoC contains one or more micro-controllers, several peripherals and embedded memories. In the software arena, there is a whole lot of embedded software that goes into products, built using these complex SoCs. In this era of consumer driven economy, all the product design groups are under a tremendous pressure to meet the aggressive time-to-market schedules and still deliver the right solution the first time. This creates a need for having a robust product flow, which enables different teams to work simultaneously and coherently. Following are some of the key activities in any product development flow. • System Engineering • Map customer requirements to design features. • Optimize design to meet the requirements in the best possible way. • Hardware design • Design, develop and integrate different Hardware (HW) or design modules/blocks • Develop reference models for validating different modules/blocks/sub-systems • Software development • Design, develop and integrate different Software (SW) modules • Develop reference models for validating these modules/sub-systems • System Validation • Build a system • Port the software onto the system • Validate the system with true system scenarios. • Customer Delivery","PeriodicalId":246670,"journal":{"name":"2009 International Symposium on VLSI Design, Automation and Test","volume":"248 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2009-04-28","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126788539","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 8

Cost efficient FEQ implementation for IEEE 802.16a OFDM transceiver 成本效益FEQ实现的IEEE 802.16a OFDM收发器

2009 International Symposium on VLSI Design, Automation and Test Pub Date : 2009-04-28 DOI: 10.1109/VDAT.2009.5158118

Chih-Hsien Lin, Yi-Hsien Lin, Chih-Feng Wu, M. Shiue, Chorng-Kuang Wang

引用次数: 1

Power and noise aware test using preliminary estimation 使用初步估计进行功率和噪声感知测试

2009 International Symposium on VLSI Design, Automation and Test Pub Date : 2009-04-28 DOI: 10.1109/VDAT.2009.5158160

K. Noda, H. Ito, K. Hatayama, T. Aikyo

引用次数: 10

Circuit acyclic clustering with input/output constraints and applications 具有输入/输出约束的电路无环聚类及其应用

2009 International Symposium on VLSI Design, Automation and Test Pub Date : 2009-04-28 DOI: 10.1109/VDAT.2009.5158107

Rung-Bin Lin, Tsung-Han Lin, Shin-An Wu

引用次数: 0

Digital PWM controller for SIDO switching converter with time-multiplexing scheme 时间复用SIDO开关变换器的数字PWM控制器

2009 International Symposium on VLSI Design, Automation and Test Pub Date : 2009-04-28 DOI: 10.1109/VDAT.2009.5158093

Chi-Wai Leng, Chun-Hung Yang, Chien-Hung Tsai

引用次数: 8

Design and analysis of 1–60GHz, RF CMOS peak detectors for LNA calibration 用于LNA校准的1-60GHz射频CMOS峰值检测器的设计与分析

2009 International Symposium on VLSI Design, Automation and Test Pub Date : 2009-04-28 DOI: 10.1109/VDAT.2009.5158157

Karthik Jayaraman, Q. Khan, P. Chiang, B. Chi

引用次数: 9

Built-in self-repair techniques for content addressable memories 内容可寻址存储器的内置自我修复技术

2009 International Symposium on VLSI Design, Automation and Test Pub Date : 2009-04-28 DOI: 10.1109/VDAT.2009.5158146

Guan-Quan Lin, Zhen-Yu Wang, Shyue-Kung Lu

引用次数: 2

Co-calibration of capacitor mismatch and comparator offset for 1-bit/stage pipelined ADC 1位/级流水线ADC电容失配和比较器偏置的联合校准

2009 International Symposium on VLSI Design, Automation and Test Pub Date : 2009-04-28 DOI: 10.1109/VDAT.2009.5158145

Xuan-Lun Huang, Ping-Ying Kang, Y. Yu, Jiun-Lang Huang

引用次数: 0

A reconfigurable architecture for entropy decoding and IDCT in H.264 H.264中熵解码和IDCT的可重构结构

2009 International Symposium on VLSI Design, Automation and Test Pub Date : 2009-04-28 DOI: 10.1109/VDAT.2009.5158149

Chia-Cheng Lo, Shang-Ta Tsai, Ming-Der Shieh

{"title":"A reconfigurable architecture for entropy decoding and IDCT in H.264","authors":"Chia-Cheng Lo, Shang-Ta Tsai, Ming-Der Shieh","doi":"10.1109/VDAT.2009.5158149","DOIUrl":"https://doi.org/10.1109/VDAT.2009.5158149","url":null,"abstract":"Reconfigurable hardware is an effective design option to cope with the increasing demands of simultaneous flexibility and computation power in system design. This paper explores techniques to combine the two entropy decoding methods, context-based adaptive binary arithmetic coding (CABAC) and context-based adaptive variable length coding (CAVLC), defined in the H.264 standard using the coarse-grain reconfigurable architecture. Coarsegrain reconfigurable architectures can provide obvious advantages over their fine-grain counterparts for some specific applications. By analyzing the similarities and differences between these two decoding processes, we show how to effectively merge CAVLC into a CABAC decoder. Experimental results reveal that about 1.5K savings in gate counts can be obtained using the proposed reconfigurable cell (RC) architecture, which corresponds to 25.4% area savings in implementing the CAVLC decoder. Moreover, using the idle time in RC arrays, the base cell can be extended to carry out the inverse discrete cosine transform with very limited overhead. Our entropy decoder design, operated in 66 MHz, can decode video sequences at MP@ Level 3.0 under the real-time constraint.","PeriodicalId":246670,"journal":{"name":"2009 International Symposium on VLSI Design, Automation and Test","volume":"43 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2009-04-28","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116279037","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 12