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2009 International Symposium on VLSI Design, Automation and Test最新文献

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A high-troughput radix-4 log-MAP decoder with low complexity LLR architecture 一种具有低复杂度LLR架构的高吞吐量基数-4 log-MAP解码器
2009 International Symposium on VLSI Design, Automation and Test Pub Date : 2009-04-28 DOI: 10.1109/VDAT.2009.5158137
Hsiang-Tsung Chuang, Kai-Hsin Tseng, W. Fang
{"title":"A high-troughput radix-4 log-MAP decoder with low complexity LLR architecture","authors":"Hsiang-Tsung Chuang, Kai-Hsin Tseng, W. Fang","doi":"10.1109/VDAT.2009.5158137","DOIUrl":"https://doi.org/10.1109/VDAT.2009.5158137","url":null,"abstract":"The throughput of turbo decoder is limited by the recursion architecture. In this paper, an improved radix-4 recursion architecture is presented. In order to decrease the critical path delay, a hybrid 4-inputs addition/subtraction structure is employed. Moreover, we present a modified trace-back architecture to decrease the hardware complexity of the log-likelihood ratios (LLR) architecture. The area of the proposed MAP decoder is 0.58 mm2 on UMC 0.13µm standard cell technology and under the worst case a maximum throughput of 600 Mbps can be achieved.","PeriodicalId":246670,"journal":{"name":"2009 International Symposium on VLSI Design, Automation and Test","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2009-04-28","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131252946","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 4
An area-efficient parallel Turbo decoder based on contention free algorithm 一种基于无争用算法的面积高效并行Turbo解码器
2009 International Symposium on VLSI Design, Automation and Test Pub Date : 2009-04-28 DOI: 10.1109/VDAT.2009.5158130
Kai-Hsin Tseng, Hsiang-Tsung Chuang, Shao-Yen Tseng, W. Fang
{"title":"An area-efficient parallel Turbo decoder based on contention free algorithm","authors":"Kai-Hsin Tseng, Hsiang-Tsung Chuang, Shao-Yen Tseng, W. Fang","doi":"10.1109/VDAT.2009.5158130","DOIUrl":"https://doi.org/10.1109/VDAT.2009.5158130","url":null,"abstract":"In this paper, a contention free algorithm for solving memory collision problem of parallel Turbo decoder architecture using the simulated annealing algorithm is presented. Furthermore, we proposed two area-efficient extrinsic memory schemes based on the parallel contention free Turbo decoder. One of the proposed schemes employs only multiple single port memories with one temporary buffer instead of the original dual port or two port memories and the other scheme further employs an additional non-linear extrinsic mapping architecture. The proposed schemes lead to approximately 37% and 46% memory area reduction, respectively, for 16-parallel Turbo decoder in comparison to the conventional dual port memory scheme under the UMC 0.13µm CMOS process.","PeriodicalId":246670,"journal":{"name":"2009 International Symposium on VLSI Design, Automation and Test","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2009-04-28","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128706929","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Visual prostheses: Current progress and challenges 视觉假体:目前的进展和挑战
2009 International Symposium on VLSI Design, Automation and Test Pub Date : 2009-04-28 DOI: 10.1109/VDAT.2009.5158111
L. Theogarajan, D. Shire, S. Kelly, J. Wyatt, J. Rizzo
{"title":"Visual prostheses: Current progress and challenges","authors":"L. Theogarajan, D. Shire, S. Kelly, J. Wyatt, J. Rizzo","doi":"10.1109/VDAT.2009.5158111","DOIUrl":"https://doi.org/10.1109/VDAT.2009.5158111","url":null,"abstract":"We have recently designed, fabricated and implanted a visual prosthesis. Animal studies show that the implant remains viable post-op. There exist numerous challenges to move the implant from the bench o the bedside and requires a concerted effort from scientists in different disciplines to come together. We hope that in the future that we will eventually take the important step being able to perform human studies to understand the efficacy of a chronic retinal implant.","PeriodicalId":246670,"journal":{"name":"2009 International Symposium on VLSI Design, Automation and Test","volume":"21 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2009-04-28","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133712456","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 4
Efficient two-layered cycle-accurate modeling technique for processor family with same instruction set architecture 同一指令集架构处理器族的高效两层周期精确建模技术
2009 International Symposium on VLSI Design, Automation and Test Pub Date : 2009-04-28 DOI: 10.1109/VDAT.2009.5158138
C. Chiang, Juinn-Dar Huang
{"title":"Efficient two-layered cycle-accurate modeling technique for processor family with same instruction set architecture","authors":"C. Chiang, Juinn-Dar Huang","doi":"10.1109/VDAT.2009.5158138","DOIUrl":"https://doi.org/10.1109/VDAT.2009.5158138","url":null,"abstract":"In this paper, we propose a new processor modeling technique that partitions a cycle-accurate model into two layers, an inner functional kernel and an outer timing shell. The kernel is an untimed but high-speed instruction set simulator (ISS) and is suitable for software development; while the timing shell provides additional timing details for cycle-accurate hardware behavior. When a new processor member is added to the family, it demands only a new timing shell because the kernel is identical to that of its ancestors sharing the same instruction set architecture (ISA). It not only helps ensure functional consistency but significantly reduces the model development time. We take two processors with a same ISA, an ARM7-like one and an ARM9-like one, as our modeling examples to demonstrate the feasibility of the proposed technique. Finally, the experimental results show that, on average our two-layered cycle-accurate model is about 30 times faster than the RTL model in simulation.","PeriodicalId":246670,"journal":{"name":"2009 International Symposium on VLSI Design, Automation and Test","volume":"8 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2009-04-28","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125839569","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
Low-voltage transformer-based CMOS VCOS and frequency dividers 基于低压变压器的CMOS VCOS和分频器
2009 International Symposium on VLSI Design, Automation and Test Pub Date : 2009-04-28 DOI: 10.1109/VDAT.2009.5158115
A. Ng, Sujiang Rong, Hui Zheng, H. Luong
{"title":"Low-voltage transformer-based CMOS VCOS and frequency dividers","authors":"A. Ng, Sujiang Rong, Hui Zheng, H. Luong","doi":"10.1109/VDAT.2009.5158115","DOIUrl":"https://doi.org/10.1109/VDAT.2009.5158115","url":null,"abstract":"Transformer feedback and coupling have been recently proposed in realizing low-voltage CMOS voltage-controlled oscillators and frequency dividers with high performance in terms of high frequency, low power, low phase noise, and good figure of merits. This paper reviews reported transformer-feedback and transformer-coupled circuit techniques and presents several designs with state-of-the-art measured performance as case studies. The key advantages as well as limitations of the techniques will also be summarized.","PeriodicalId":246670,"journal":{"name":"2009 International Symposium on VLSI Design, Automation and Test","volume":"27 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2009-04-28","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125915909","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
VLSI design of spread spectrum encoding low power RFID tag baseband processor 扩频编码低功耗RFID标签基带处理器的VLSI设计
2009 International Symposium on VLSI Design, Automation and Test Pub Date : 2009-04-28 DOI: 10.1109/VDAT.2009.5158127
Zhu Qiu-ling, Zhang Chun, Wang Xiaohui, W. Ziqiang, Li Fule, W. Zhihua
{"title":"VLSI design of spread spectrum encoding low power RFID tag baseband processor","authors":"Zhu Qiu-ling, Zhang Chun, Wang Xiaohui, W. Ziqiang, Li Fule, W. Zhihua","doi":"10.1109/VDAT.2009.5158127","DOIUrl":"https://doi.org/10.1109/VDAT.2009.5158127","url":null,"abstract":"Due to the weak signal energy of the backscatter link, traditional RFID communication is easily affected by noises, interferences, and interceptions from the environment. To solve the problem, a novel passive UHF RFID tag baseband processor enhanced with spread spectrum technique is presented in this paper. In addition, power-saving strategies are proposed to reduce the power consumption of the tag. Simulated results show that spread spectrum approach largely reduces the Bit Error Rate and improves system's reliability and security. Finally, a complete RFID tag with the proposed baseband processor was designed and fabricated using 0.18um 1P6M CMOS technology. From the measurement result, the overall power consumption of the baseband processor is about 8.8uW at the minimum voltage of 1.04V.","PeriodicalId":246670,"journal":{"name":"2009 International Symposium on VLSI Design, Automation and Test","volume":"71 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2009-04-28","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127997324","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
A 1.55ns 0.015 mm2 64-bit quad number comparator 1.55ns 0.015 mm2 64位四位数比较器
2009 International Symposium on VLSI Design, Automation and Test Pub Date : 2009-04-28 DOI: 10.1109/VDAT.2009.5158150
Minsu Kim, Joo-Young Kim, H. Yoo
{"title":"A 1.55ns 0.015 mm2 64-bit quad number comparator","authors":"Minsu Kim, Joo-Young Kim, H. Yoo","doi":"10.1109/VDAT.2009.5158150","DOIUrl":"https://doi.org/10.1109/VDAT.2009.5158150","url":null,"abstract":"This paper proposes a fast and small area 64-bit quad binary number comparator. Proposed bit-wise comparing logic chain (BCLC) and sequential strobes (SS) scheme enables 1.55ns 64-bit quad binary number comparison, which is 16% improvement compared to conventional comparator. With the help of BCLC and SS scheme, the proposed quad binary number comparator consumes 0.015 mm2 in 0.18 um CMOS technology. Compared to previous works, the proposed comparator shows 9% reduction of transistor count and 13% area reduction.","PeriodicalId":246670,"journal":{"name":"2009 International Symposium on VLSI Design, Automation and Test","volume":"95 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2009-04-28","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123324221","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 6
Logic synthesis for better than worst-case designs 逻辑综合优于最坏情况的设计
2009 International Symposium on VLSI Design, Automation and Test Pub Date : 2009-04-28 DOI: 10.1109/VDAT.2009.5158121
J. Cong, Kirill Minkovich
{"title":"Logic synthesis for better than worst-case designs","authors":"J. Cong, Kirill Minkovich","doi":"10.1109/VDAT.2009.5158121","DOIUrl":"https://doi.org/10.1109/VDAT.2009.5158121","url":null,"abstract":"In this paper we present a novel metric for measuring and optimizing the performance of circuits that operate with the clock period smaller than the worst-case delay. In particular, we developed an efficient logic optimization operation “balance” and a library mapping algorithm named BTWLibMap. Together they are able to reduce the probability of a timing error by 2.3X while only incurring a 4% area overhead.","PeriodicalId":246670,"journal":{"name":"2009 International Symposium on VLSI Design, Automation and Test","volume":"89 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2009-04-28","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126500546","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 21
Scalable and low cost design approach for variable block size motion estimation (VBSME) 可变块大小运动估计(VBSME)的可扩展低成本设计方法
2009 International Symposium on VLSI Design, Automation and Test Pub Date : 2009-04-28 DOI: 10.1109/VDAT.2009.5158147
H. Parandeh-Afshar, P. Brisk, P. Ienne
{"title":"Scalable and low cost design approach for variable block size motion estimation (VBSME)","authors":"H. Parandeh-Afshar, P. Brisk, P. Ienne","doi":"10.1109/VDAT.2009.5158147","DOIUrl":"https://doi.org/10.1109/VDAT.2009.5158147","url":null,"abstract":"Variable block size motion estimation (VBSME) in state-of-the-art video coding standards is one of the key features which improves the coding efficiency significantly compared to the previous standards. VBSME hardware design is a challenging task due to its complexity. The processing power requirement for VBSME depends on many factors such as frame size, frame rate and search area. In video coding standards these features are allowed to vary, depending on the requirements of the application. In this paper, a scalable and low cost approach is proposed for designing the VBSME which allows us to tailor the architecture for different applications requirements and implementation targets efficiently. This approach can be used in redesigning of current VBSME architectures to improve their scalability and reduce their design costs. Moreover, as this technique is not block size dependent, it can be employed in designing future coding standards with different block sizes.","PeriodicalId":246670,"journal":{"name":"2009 International Symposium on VLSI Design, Automation and Test","volume":"47 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2009-04-28","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122538207","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 5
A current compensated reference oscillator 一个电流补偿基准振荡器
2009 International Symposium on VLSI Design, Automation and Test Pub Date : 2009-04-28 DOI: 10.1109/VDAT.2009.5158112
Wan-Jing Li, Soon-Jyh Chang, Ying-Zu Lin
{"title":"A current compensated reference oscillator","authors":"Wan-Jing Li, Soon-Jyh Chang, Ying-Zu Lin","doi":"10.1109/VDAT.2009.5158112","DOIUrl":"https://doi.org/10.1109/VDAT.2009.5158112","url":null,"abstract":"This paper reports a reliable current compensated reference oscillator without any BJT or external component. To maintain a stable oscillation frequency, the discharging current of the proposed architecture varies with process, supply voltage and temperature (PVT) variations. Fabricated in a 0.18-µm digital CMOS process, this oscillator consumes 0.5 mW from a 1.8..V supply. The post-simulation results show the worst case is 12%. From 500 times Monte Carlo simulation results, the frequency variations are all limited within ±3%. The measurement result of ten samples at room temperature with 10% supply voltage deviation shows variation within ±10%. The maximum variation is –10.19% with process and supply voltage variations from measurement results.","PeriodicalId":246670,"journal":{"name":"2009 International Symposium on VLSI Design, Automation and Test","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2009-04-28","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125375795","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 3
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