A 1.55ns 0.015 mm2 64-bit quad number comparator

Abstract

This paper proposes a fast and small area 64-bit quad binary number comparator. Proposed bit-wise comparing logic chain (BCLC) and sequential strobes (SS) scheme enables 1.55ns 64-bit quad binary number comparison, which is 16% improvement compared to conventional comparator. With the help of BCLC and SS scheme, the proposed quad binary number comparator consumes 0.015 mm2 in 0.18 um CMOS technology. Compared to previous works, the proposed comparator shows 9% reduction of transistor count and 13% area reduction.