{"title":"Power and noise aware test using preliminary estimation","authors":"K. Noda, H. Ito, K. Hatayama, T. Aikyo","doi":"10.1109/VDAT.2009.5158160","DOIUrl":null,"url":null,"abstract":"Issues on power consumption and IR-drop in testing become serious problems. Some troubles, such as tester fails due to too much power consumption or IR-drop, test escapes due to slowed clock cycle, and so on, can happen in test floors. In this paper, we propose a power and noise aware scan test method. In the method, power-aware DFT and power-aware ATPG are executed based on the preliminary power/noise estimation for test. Experimental results illustrate the effect of reducing IR-drop for both shift and capture mode in scan test.","PeriodicalId":246670,"journal":{"name":"2009 International Symposium on VLSI Design, Automation and Test","volume":"17 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2009-04-28","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"10","resultStr":null,"platform":"Semanticscholar","paperid":null,"PeriodicalName":"2009 International Symposium on VLSI Design, Automation and Test","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/VDAT.2009.5158160","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 10
Abstract
Issues on power consumption and IR-drop in testing become serious problems. Some troubles, such as tester fails due to too much power consumption or IR-drop, test escapes due to slowed clock cycle, and so on, can happen in test floors. In this paper, we propose a power and noise aware scan test method. In the method, power-aware DFT and power-aware ATPG are executed based on the preliminary power/noise estimation for test. Experimental results illustrate the effect of reducing IR-drop for both shift and capture mode in scan test.