ESSCIRC Conference 2016: 42nd European Solid-State Circuits Conference最新文献

A 433 MHz 54 µW OOK/FSK/PSK compatible wake-up receiver with 11 µW low-power mode based on injection-locked oscillator 433 MHz 54µW OOK/FSK/PSK兼容唤醒接收器，11µW低功耗模式，基于注入锁定振荡器

ESSCIRC Conference 2016: 42nd European Solid-State Circuits Conference Pub Date : 2016-10-18 DOI: 10.1109/ESSCIRC.2016.7598261

Shih-En Chen, Kuang-Wei Cheng

引用次数: 12

Experimental demonstration of a nanoelectromechanical switch-based logic library including sequential and combinational gates 基于顺序门和组合门的纳米机电开关逻辑库的实验演示

ESSCIRC Conference 2016: 42nd European Solid-State Circuits Conference Pub Date : 2016-10-18 DOI: 10.1109/ESSDERC.2016.7599586

C. Ayala, A. Bazigos, D. Grogg, U. Drechsler, C. Hagleitner

引用次数: 0

A 1 Tb/s/mm2 inductive-coupling side-by-side chip link 一个1tb /s/mm2电感耦合并排芯片链路

ESSCIRC Conference 2016: 42nd European Solid-State Circuits Conference Pub Date : 2016-10-18 DOI: 10.1109/ESSCIRC.2016.7598343

S. Hasegawa, J. Kadomoto, Atsutake Kosuge, T. Kuroda

引用次数: 4

Motion-vector estimation and cognitive classification on an image sensor/processor 3D stacked system featuring ThruChip interfaces 基于ThruChip接口的图像传感器/处理器3D堆叠系统的运动矢量估计和认知分类

ESSCIRC Conference 2016: 42nd European Solid-State Circuits Conference Pub Date : 2016-10-18 DOI: 10.1109/ESSCIRC.2016.7598253

T. Asai, Masafumi Mori, T. Itou, Yasuhiro Take, M. Ikebe, T. Kuroda, M. Motomura

引用次数: 0

A 5-50 Gb/s quarter rate transmitter with a 4-tap multiple-MUX based FFE in 65 nm CMOS 一个5- 50gb /s的四分之一速率发射机，在65nm CMOS中基于4分路多mux的FFE

ESSCIRC Conference 2016: 42nd European Solid-State Circuits Conference Pub Date : 2016-09-12 DOI: 10.1109/ESSCIRC.2016.7598303

Xuqiang Zheng, Chun Zhang, Fangxu Lv, Feng Zhao, Shigang Yue, Ziqiang Wang, Fule Li, Zhihua Wang

引用次数: 11

High-voltage tolerant bi-state self-biasing output driver using cascade complementary latches in twin-well CMOS technology 采用级联互补锁存器的双阱CMOS技术的高容压双态自偏置输出驱动器

ESSCIRC Conference 2016: 42nd European Solid-State Circuits Conference Pub Date : 2016-09-01 DOI: 10.1109/ESSCIRC.2016.7598297

R. Jansen, S. Lindner

{"title":"High-voltage tolerant bi-state self-biasing output driver using cascade complementary latches in twin-well CMOS technology","authors":"R. Jansen, S. Lindner","doi":"10.1109/ESSCIRC.2016.7598297","DOIUrl":"https://doi.org/10.1109/ESSCIRC.2016.7598297","url":null,"abstract":"The design of a bi-state output buffer that can handle 5 times the supply voltage is presented. The use of self-biasing stacked devices driven by a cascade of complementary latches allows all devices to operate within the limits set by the technology, thus minimising any hot carrier injection and dielectric stress degradation. The presented voltage extension technique is scalable to larger and smaller external voltages and suitable for all twin-well technology feature sizes. The technique using the cascade of complementary latches is applied to the realization of a CAN output driver in a digital twin-well double-oxide 180nm technology featuring both 1.8V 180nm and 3.3V 350nm CMOS devices. The CAN driver consists of two bi-state drivers, which are both in high-impedance state during the CAN recessive state and in the high and respectively low state for the CAN dominant state. The realized prototype driver can handle external voltages between -3V and 16V and exhibits a 1.5V differential output swing on a 60Ohm load over the military temperature range compliant to the CAN automotive standard. To the best of our knowledge this is also the first realization of a CAN driver in a low-voltage digital CMOS technology.","PeriodicalId":246471,"journal":{"name":"ESSCIRC Conference 2016: 42nd European Solid-State Circuits Conference","volume":"3 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"117051164","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 2

A recursive house-of-cards digital power amplifier employing a λ/4-less Doherty power combiner in 65nm CMOS 采用λ/4-less Doherty功率组合器的65纳米CMOS递归卡片屋数字功率放大器

ESSCIRC Conference 2016: 42nd European Solid-State Circuits Conference Pub Date : 2016-09-01 DOI: 10.1109/ESSCIRC.2016.7598274

Loai G. Salem, J. Buckwalter, P. Mercier

引用次数: 5

A 2.6mm2 0.19nJ/pixel VP9 and multi-standard decoder LSI for Android 4K TV applications 2.6mm2 0.19nJ/pixel VP9和多标准解码器LSI，适用于Android 4K电视应用

ESSCIRC Conference 2016: 42nd European Solid-State Circuits Conference Pub Date : 2016-09-01 DOI: 10.1109/ESSCIRC.2016.7598254

Chi-Cheng Ju, Tsu-Ming Liu, Yung-Chang Chang, Chih-Ming Wang, Chia-Yun Cheng, Hue-Min Lin, Chun-Chia Chen, Min-Hao Chiu, P. Chao, Ming-Long Wu, Meng-Jye Hu, Sheng-Jen Wang, Che-Hong Chen, Shun-Hsiang Chuang, Hsiu-Yi Lin, Fu-Chun Yeh, C. Kao, Yi-Chang Chen, Chia-Lin Ho, Yen-Chao Huang, Hsiao-En Chen, Chih-Wen Yang, Hsuan-Wen Peng

{"title":"A 2.6mm2 0.19nJ/pixel VP9 and multi-standard decoder LSI for Android 4K TV applications","authors":"Chi-Cheng Ju, Tsu-Ming Liu, Yung-Chang Chang, Chih-Ming Wang, Chia-Yun Cheng, Hue-Min Lin, Chun-Chia Chen, Min-Hao Chiu, P. Chao, Ming-Long Wu, Meng-Jye Hu, Sheng-Jen Wang, Che-Hong Chen, Shun-Hsiang Chuang, Hsiu-Yi Lin, Fu-Chun Yeh, C. Kao, Yi-Chang Chen, Chia-Lin Ho, Yen-Chao Huang, Hsiao-En Chen, Chih-Wen Yang, Hsuan-Wen Peng","doi":"10.1109/ESSCIRC.2016.7598254","DOIUrl":"https://doi.org/10.1109/ESSCIRC.2016.7598254","url":null,"abstract":"A lower power and area efficient VP9 and multi-standard video decoder chip is first-reported for Android 4K TV. It supports prevalent MPEG-x, VP-x, RMx, WMV-x and H.26x series video standards in a single chip. Three high-throughput techniques, look-ahead re-mapping, early stage pipeline and dynamic-scheduled bus translation, are proposed. They cuts the processing times by 51.2% compared to the state-of-the-art design [4]. Moreover, two area-efficient techniques, hybrid backward probability update and tile-to-raster scan ordering, are designed to reduce the internal memory size by 10%. A mass-production chip is fabricated in a 28nm CMOS technology with an energy efficiency of 0.19nJ/pixel and an area of 2.6mm2. Compared to the dual-core decoder design [4], this work achieves the identical performance (4K@60fps) with single core which cut one-half of chip area.","PeriodicalId":246471,"journal":{"name":"ESSCIRC Conference 2016: 42nd European Solid-State Circuits Conference","volume":"48 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124958078","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 1

A ZVS resonant receiver with maximum efficiency tracking for device-to-device wireless charging 一种ZVS谐振接收器，具有设备对设备无线充电的最高效率跟踪

ESSCIRC Conference 2016: 42nd European Solid-State Circuits Conference Pub Date : 2016-09-01 DOI: 10.1109/ESSCIRC.2016.7598305

Nachiket V. Desai, A. Chandrakasan

引用次数: 6

Polymer Microwave Fibers: A blend of RF, copper and optical communication 聚合物微波光纤:射频、铜和光通信的混合物

ESSCIRC Conference 2016: 42nd European Solid-State Circuits Conference Pub Date : 2016-09-01 DOI: 10.1109/ESSCIRC.2016.7598233

P. Reynaert, M. Tytgat, Wouter Volkaerts, Alexander Standaert, Yang Zhang, Maxime De Wit, Niels Van Thienen

引用次数: 22