S. Hasegawa, J. Kadomoto, Atsutake Kosuge, T. Kuroda
{"title":"一个1tb /s/mm2电感耦合并排芯片链路","authors":"S. Hasegawa, J. Kadomoto, Atsutake Kosuge, T. Kuroda","doi":"10.1109/ESSCIRC.2016.7598343","DOIUrl":null,"url":null,"abstract":"An inductive coupling technique for wireless interconnection of side-by-side chips within a package is presented. Data is transferred by using changes in magnetic field that occur when the current in coils on the chips is switched off. The circuit layout area and power consumption of transceivers have respectively been reduced to 1/3 and 1/6. A world-leading transmission rate of 1 Tb/s/mm2, which is faster by a factor of 3, has been achieved with a 0.18 μm CMOS test chip.","PeriodicalId":246471,"journal":{"name":"ESSCIRC Conference 2016: 42nd European Solid-State Circuits Conference","volume":"134 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2016-10-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"4","resultStr":"{\"title\":\"A 1 Tb/s/mm2 inductive-coupling side-by-side chip link\",\"authors\":\"S. Hasegawa, J. Kadomoto, Atsutake Kosuge, T. Kuroda\",\"doi\":\"10.1109/ESSCIRC.2016.7598343\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"An inductive coupling technique for wireless interconnection of side-by-side chips within a package is presented. Data is transferred by using changes in magnetic field that occur when the current in coils on the chips is switched off. The circuit layout area and power consumption of transceivers have respectively been reduced to 1/3 and 1/6. A world-leading transmission rate of 1 Tb/s/mm2, which is faster by a factor of 3, has been achieved with a 0.18 μm CMOS test chip.\",\"PeriodicalId\":246471,\"journal\":{\"name\":\"ESSCIRC Conference 2016: 42nd European Solid-State Circuits Conference\",\"volume\":\"134 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"2016-10-18\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"4\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"ESSCIRC Conference 2016: 42nd European Solid-State Circuits Conference\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/ESSCIRC.2016.7598343\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"ESSCIRC Conference 2016: 42nd European Solid-State Circuits Conference","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/ESSCIRC.2016.7598343","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
A 1 Tb/s/mm2 inductive-coupling side-by-side chip link
An inductive coupling technique for wireless interconnection of side-by-side chips within a package is presented. Data is transferred by using changes in magnetic field that occur when the current in coils on the chips is switched off. The circuit layout area and power consumption of transceivers have respectively been reduced to 1/3 and 1/6. A world-leading transmission rate of 1 Tb/s/mm2, which is faster by a factor of 3, has been achieved with a 0.18 μm CMOS test chip.