{"title":"采用λ/4-less Doherty功率组合器的65纳米CMOS递归卡片屋数字功率放大器","authors":"Loai G. Salem, J. Buckwalter, P. Mercier","doi":"10.1109/ESSCIRC.2016.7598274","DOIUrl":null,"url":null,"abstract":"This paper presents a DC-RF power inverter that efficiently synthesizes high-voltage RF waveforms directly from a battery voltage using thin-oxide CMOS switches. Instead of stacking transistors or employing large inductive transformation ratios, high output power is generated by switching individual class-D power amplifier (PA) cells in a 2-phase house-of-cards (HoC) topology to provide voltage addition of the cells outputs without exceeding device voltage ratings, effectively resulting in a solid-state RF impedance transformer. High-efficiency at backoff is then achieved by capacitively combining the output of two HoC networks nominally set to generate different amplitudes, enabling voltage-mode Doherty-like backoff without a bulky transmission line. The PA is implemented in 65nm bulk LP CMOS, operates from 4.8V, and provides a battery-to-RF efficiency above 40% at both 23dBm and 6dB backoff at 720MHz.","PeriodicalId":246471,"journal":{"name":"ESSCIRC Conference 2016: 42nd European Solid-State Circuits Conference","volume":"35 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2016-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"5","resultStr":"{\"title\":\"A recursive house-of-cards digital power amplifier employing a λ/4-less Doherty power combiner in 65nm CMOS\",\"authors\":\"Loai G. Salem, J. Buckwalter, P. Mercier\",\"doi\":\"10.1109/ESSCIRC.2016.7598274\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"This paper presents a DC-RF power inverter that efficiently synthesizes high-voltage RF waveforms directly from a battery voltage using thin-oxide CMOS switches. Instead of stacking transistors or employing large inductive transformation ratios, high output power is generated by switching individual class-D power amplifier (PA) cells in a 2-phase house-of-cards (HoC) topology to provide voltage addition of the cells outputs without exceeding device voltage ratings, effectively resulting in a solid-state RF impedance transformer. High-efficiency at backoff is then achieved by capacitively combining the output of two HoC networks nominally set to generate different amplitudes, enabling voltage-mode Doherty-like backoff without a bulky transmission line. The PA is implemented in 65nm bulk LP CMOS, operates from 4.8V, and provides a battery-to-RF efficiency above 40% at both 23dBm and 6dB backoff at 720MHz.\",\"PeriodicalId\":246471,\"journal\":{\"name\":\"ESSCIRC Conference 2016: 42nd European Solid-State Circuits Conference\",\"volume\":\"35 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"2016-09-01\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"5\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"ESSCIRC Conference 2016: 42nd European Solid-State Circuits Conference\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/ESSCIRC.2016.7598274\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"ESSCIRC Conference 2016: 42nd European Solid-State Circuits Conference","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/ESSCIRC.2016.7598274","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
A recursive house-of-cards digital power amplifier employing a λ/4-less Doherty power combiner in 65nm CMOS
This paper presents a DC-RF power inverter that efficiently synthesizes high-voltage RF waveforms directly from a battery voltage using thin-oxide CMOS switches. Instead of stacking transistors or employing large inductive transformation ratios, high output power is generated by switching individual class-D power amplifier (PA) cells in a 2-phase house-of-cards (HoC) topology to provide voltage addition of the cells outputs without exceeding device voltage ratings, effectively resulting in a solid-state RF impedance transformer. High-efficiency at backoff is then achieved by capacitively combining the output of two HoC networks nominally set to generate different amplitudes, enabling voltage-mode Doherty-like backoff without a bulky transmission line. The PA is implemented in 65nm bulk LP CMOS, operates from 4.8V, and provides a battery-to-RF efficiency above 40% at both 23dBm and 6dB backoff at 720MHz.