A 2.6mm2 0.19nJ/pixel VP9 and multi-standard decoder LSI for Android 4K TV applications

ESSCIRC Conference 2016: 42nd European Solid-State Circuits Conference Pub Date : 2016-09-01 DOI:10.1109/ESSCIRC.2016.7598254

Chi-Cheng Ju, Tsu-Ming Liu, Yung-Chang Chang, Chih-Ming Wang, Chia-Yun Cheng, Hue-Min Lin, Chun-Chia Chen, Min-Hao Chiu, P. Chao, Ming-Long Wu, Meng-Jye Hu, Sheng-Jen Wang, Che-Hong Chen, Shun-Hsiang Chuang, Hsiu-Yi Lin, Fu-Chun Yeh, C. Kao, Yi-Chang Chen, Chia-Lin Ho, Yen-Chao Huang, Hsiao-En Chen, Chih-Wen Yang, Hsuan-Wen Peng

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引用次数: 1

Abstract

A lower power and area efficient VP9 and multi-standard video decoder chip is first-reported for Android 4K TV. It supports prevalent MPEG-x, VP-x, RMx, WMV-x and H.26x series video standards in a single chip. Three high-throughput techniques, look-ahead re-mapping, early stage pipeline and dynamic-scheduled bus translation, are proposed. They cuts the processing times by 51.2% compared to the state-of-the-art design [4]. Moreover, two area-efficient techniques, hybrid backward probability update and tile-to-raster scan ordering, are designed to reduce the internal memory size by 10%. A mass-production chip is fabricated in a 28nm CMOS technology with an energy efficiency of 0.19nJ/pixel and an area of 2.6mm2. Compared to the dual-core decoder design [4], this work achieves the identical performance (4K@60fps) with single core which cut one-half of chip area.

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2.6mm2 0.19nJ/pixel VP9和多标准解码器LSI，适用于Android 4K电视应用

首次报道了一种用于Android 4K电视的低功耗多标准VP9视频解码器芯片。它在一个芯片上支持流行的MPEG-x、VP-x、RMx、WMV-x和H.26x系列视频标准。提出了三种高吞吐量技术:前瞻性重映射、早期管道和动态调度总线转换。与最先进的设计相比，它们将处理时间缩短了51.2%[4]。此外，混合后向概率更新和瓦片到栅格扫描排序两种面积效率技术的设计可将内存大小减少10%。量产芯片采用28nm CMOS工艺，能量效率为0.19nJ/pixel，面积为2.6mm2。与双核解码器设计[4]相比，这项工作实现了与单核相同的性能(4K@60fps)，减少了一半的芯片面积。

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ESSCIRC Conference 2016: 42nd European Solid-State Circuits Conference

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