2009 IEEE 15th International Mixed-Signals, Sensors, and Systems Test Workshop最新文献

Mixed-signal testing using Walsh functions 混合信号测试使用沃尔什函数

2009 IEEE 15th International Mixed-Signals, Sensors, and Systems Test Workshop Pub Date : 2009-06-10 DOI: 10.1109/IMS3TW.2009.5158700

Aurelien Tcheghoyz, S. Sattler, Helmut Graby

引用次数: 2

BIST-assisted power aware self healing RF circuits bist辅助功率感知自修复射频电路

2009 IEEE 15th International Mixed-Signals, Sensors, and Systems Test Workshop Pub Date : 2009-06-10 DOI: 10.1109/IMS3TW.2009.5158691

S. Devarakond, Vishwanath Natarajan, Shreyas Sen, A. Chatterjee

引用次数: 11

TAC: Testing time reduction for digitally-calibrated designs TAC:减少数字校准设计的测试时间

2009 IEEE 15th International Mixed-Signals, Sensors, and Systems Test Workshop Pub Date : 2009-06-10 DOI: 10.1109/IMS3TW.2009.5158690

Hsiu-Ming Chang, K. Cheng

{"title":"TAC: Testing time reduction for digitally-calibrated designs","authors":"Hsiu-Ming Chang, K. Cheng","doi":"10.1109/IMS3TW.2009.5158690","DOIUrl":"https://doi.org/10.1109/IMS3TW.2009.5158690","url":null,"abstract":"For digitally-calibrated analog, mixed-signal and radio-frequency (AMS/RF) circuits, it is desirable to stop the calibration process as soon as it reaches convergence. Such a strategy can avoid wasting unnecessary calibration time and ensure high calibration quality during production testing. However, due to the lack of systematic methods for convergence detection, existing digitally-calibrated designs simply allot a fixed and sufficiently long period of time for calibration. In this paper, we propose a method to reduce testing time by terminating calibration at convergence for circuits that employ the least-mean-square (LMS) algorithm for built-in calibration. We observe the fluctuation range of the tap coefficients in the digital calibration unit to determine whether the convergence criteria are met and subsequently terminate the calibration process. We conduct two case studies - a digitally-calibrated pipelined ADC and a digitally-calibrated image-reject receiver - to demonstrate the generality and effectiveness of our proposed method. In comparison with the existing termination policy, our proposed method, on average, can reduce the calibration time by 70%.","PeriodicalId":246363,"journal":{"name":"2009 IEEE 15th International Mixed-Signals, Sensors, and Systems Test Workshop","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2009-06-10","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126802089","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 5

Dependable reconfigurable multi-sensor poles for security 安全可靠的可重构多传感器极点

2009 IEEE 15th International Mixed-Signals, Sensors, and Systems Test Workshop Pub Date : 2009-06-10 DOI: 10.1109/IMS3TW.2009.5158681

H. Kerkhoff

引用次数: 3

Demonstration of 20 Gbps digital test signal synthesis using SiGe and InP logic 用SiGe和InP逻辑合成20gbps数字测试信号的演示

2009 IEEE 15th International Mixed-Signals, Sensors, and Systems Test Workshop Pub Date : 2009-06-10 DOI: 10.1109/IMS3TW.2009.5158693

D. Keezer, C. Gray, D. Minier, P. Ducharme

引用次数: 3

Accurate ADC dynamic testing by means of the three-parameter sine-fit algorithm 采用三参数正弦拟合算法对ADC进行精确动态测试

2009 IEEE 15th International Mixed-Signals, Sensors, and Systems Test Workshop Pub Date : 2009-06-10 DOI: 10.1109/IMS3TW.2009.5158682

D. Belega, D. Dallet

引用次数: 4

Vector based Analog to Digital Converter sequential testing methodology to minimize ATE memory and analysis requirements 基于矢量的模数转换器顺序测试方法，最大限度地减少ATE内存和分析要求

2009 IEEE 15th International Mixed-Signals, Sensors, and Systems Test Workshop Pub Date : 2009-06-10 DOI: 10.1109/IMS3TW.2009.5158697

S. Dasnurkar, J. Abraham

{"title":"Vector based Analog to Digital Converter sequential testing methodology to minimize ATE memory and analysis requirements","authors":"S. Dasnurkar, J. Abraham","doi":"10.1109/IMS3TW.2009.5158697","DOIUrl":"https://doi.org/10.1109/IMS3TW.2009.5158697","url":null,"abstract":"Mixed signal circuits typically require more complex specification based testing as compared to digital circuits, which can be completely tested with structural or simple functional tests. Due to the analog nature of some of the internal nodes and external signals in mixed signal circuits, qualitative functional tests may be required to assure circuit performance at all operating points. Mixed signal blocks such as Analog to Digital Converters (ADC) and Digital to Analog Converters (DAC) act as interfaces between the digital processing modules of the System on a Chip (SoC) and interfacing analog domains. These converters are increasingly common on SoCs due to ever-increasing presence of real world analog signals that use the processing capabilities of the digital blocks. High volume production testing of these mixed-signal components is inefficient due to test complications, resulting in the use of high-performance Automatic Test Equipment (ATE). While various Built-in Self Test (BiST) schemes are proposed to provide the analog test stimulus, the conventional histogram analysis method is still in use for the majority of ADC testing applications. We review a proposal for ADC output test involving a functional pattern, effectively resulting in a real-time-code-analysis. Memory and processing constraints for the ATE are reduced as this vector based method is not ATE memory intensive while providing an output quality measure identical to the conventional histogram method.","PeriodicalId":246363,"journal":{"name":"2009 IEEE 15th International Mixed-Signals, Sensors, and Systems Test Workshop","volume":"23 17 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2009-06-10","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122105134","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 5

Estimation of RF PA nonlinearities after cross-correlating power supply current and output voltage 电源电流和输出电压互相关后射频放大器非线性估计

2009 IEEE 15th International Mixed-Signals, Sensors, and Systems Test Workshop Pub Date : 2009-06-10 DOI: 10.1109/IMS3TW.2009.5158689

R. Veiga, P. Mota, J. M. da Silva

引用次数: 1

Surface plasmon resonance biosensor based on Vroman effect : Towards cancer biomarker detection 基于Vroman效应的表面等离子体共振生物传感器:面向癌症生物标志物检测

2009 IEEE 15th International Mixed-Signals, Sensors, and Systems Test Workshop Pub Date : 2009-06-10 DOI: 10.1109/IMS3TW.2009.5158683

Seokheun Choi, J. Chae

{"title":"Surface plasmon resonance biosensor based on Vroman effect : Towards cancer biomarker detection","authors":"Seokheun Choi, J. Chae","doi":"10.1109/IMS3TW.2009.5158683","DOIUrl":"https://doi.org/10.1109/IMS3TW.2009.5158683","url":null,"abstract":"We report a new sensing technique of proteins using the Vroman effect in a microfluidic device. The sensor relies on the competitive nature of protein adsorption onto a surface, directly depending upon protein's adsorption strength. The sensor uses SPR (surface plasmon resonance) for highly sensitive biomolecular interactions detection and the Vroman effect for highly selective detection. A target protein displaces a pre-adsorbed weak-affinity protein; however a pre-adsorbed strong-affinity protein is not displaced by the target protein. In a microfluidic device, we engineer two gold surfaces covered by two known proteins. The sensor allows selective protein detection by being displaced by a target protein on only one of the surfaces. The SPR sensorgrams show that four different human serum proteins, albumin (Alb), immunoglobulin G (IgG), fibrinogen (Fib), and thyroglobulin (Tg) have different adsorption strengths to the surface and the competitive adsorption of individuals controls the exchange sequence. Based on the exchange reaction, we demonstrate that the sensor has a high selectivity for Tg which is a thyroid cancer biomarker. By using the technique, we bypass having to rely on bio-receptors and their attachment to transducers, a process known to be complex and time-consuming.","PeriodicalId":246363,"journal":{"name":"2009 IEEE 15th International Mixed-Signals, Sensors, and Systems Test Workshop","volume":"43 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2009-06-10","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125604277","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 9

Closed-loop Built in Self Test for PLL production testing with minimal tester resources 闭环内置自检锁相环生产测试与最少的测试资源

2009 IEEE 15th International Mixed-Signals, Sensors, and Systems Test Workshop Pub Date : 2009-06-10 DOI: 10.1109/IMS3TW.2009.5158687

S. Dasnurkar, J. Abraham

{"title":"Closed-loop Built in Self Test for PLL production testing with minimal tester resources","authors":"S. Dasnurkar, J. Abraham","doi":"10.1109/IMS3TW.2009.5158687","DOIUrl":"https://doi.org/10.1109/IMS3TW.2009.5158687","url":null,"abstract":"Phase Locked Loops (PLLs) are extensively used in modern System on a Chip (SoC) modules for generating timing, clock signal recovery and to provide a timing reference for communication interfaces. Due to their use in crucial and omnipresent applications, PLLs are the only mixed signal components on many otherwise digital blocks. The mixed signal nature makes testing of PLLs complicated as the output test requirements include non-digital parameters such as phase error, lock time, jitter along with the typical frequency locking test. Automatic Test Equipment (ATE) resources needed for these added parameters may require the use of a higher-end ATE for an otherwise digital block, driving up the production test costs. Built in Self Test (BiST) approaches for PLLs need to be carefully designed due to the load-sensitive nature of the internal analog nodes as well as sensitivity of the feedback path to any added delays by the BiST overhead. Our scheme proposes a mixed-signal closed loop complete test solution for a PLL by injecting a BiST signal at non-sensitive internal nodes and observing a low frequency(LF)/DC output in order to perform a pass/fail decision on the PLL. The goal of this scheme is to enable complete production quality at-speed testing of a PLL using minimal ATE resources.","PeriodicalId":246363,"journal":{"name":"2009 IEEE 15th International Mixed-Signals, Sensors, and Systems Test Workshop","volume":"15 9","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2009-06-10","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"120903377","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 4