{"title":"混合信号测试使用沃尔什函数","authors":"Aurelien Tcheghoyz, S. Sattler, Helmut Graby","doi":"10.1109/IMS3TW.2009.5158700","DOIUrl":null,"url":null,"abstract":"The paper suggests an accurate and simple approach to frequency testing of analog and mixed-signal circuits in the digital domain. The method is aimed at reducing the cost of test (CoT) for systems-on-chip (SoC) devices while taking advantage of digital resources already present in the SoC devices, and using low-cost digital testers, respectively. It is based on Walsh functions, the Fast Walsh Transformation (FWT) and a simple digital processing algorithm. Since both test signal generation and test response analysis are performed on-chip, it leads to an efficient and robust approach very suitable to built-in self-test (BIST) applications, too. Considerations for on-chip implementation are also addressed together with simulation and experimental results that validate the feasibility of the proposed approach.","PeriodicalId":246363,"journal":{"name":"2009 IEEE 15th International Mixed-Signals, Sensors, and Systems Test Workshop","volume":"60 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2009-06-10","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"2","resultStr":"{\"title\":\"Mixed-signal testing using Walsh functions\",\"authors\":\"Aurelien Tcheghoyz, S. Sattler, Helmut Graby\",\"doi\":\"10.1109/IMS3TW.2009.5158700\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"The paper suggests an accurate and simple approach to frequency testing of analog and mixed-signal circuits in the digital domain. The method is aimed at reducing the cost of test (CoT) for systems-on-chip (SoC) devices while taking advantage of digital resources already present in the SoC devices, and using low-cost digital testers, respectively. It is based on Walsh functions, the Fast Walsh Transformation (FWT) and a simple digital processing algorithm. Since both test signal generation and test response analysis are performed on-chip, it leads to an efficient and robust approach very suitable to built-in self-test (BIST) applications, too. Considerations for on-chip implementation are also addressed together with simulation and experimental results that validate the feasibility of the proposed approach.\",\"PeriodicalId\":246363,\"journal\":{\"name\":\"2009 IEEE 15th International Mixed-Signals, Sensors, and Systems Test Workshop\",\"volume\":\"60 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"2009-06-10\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"2\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"2009 IEEE 15th International Mixed-Signals, Sensors, and Systems Test Workshop\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/IMS3TW.2009.5158700\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"2009 IEEE 15th International Mixed-Signals, Sensors, and Systems Test Workshop","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/IMS3TW.2009.5158700","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
The paper suggests an accurate and simple approach to frequency testing of analog and mixed-signal circuits in the digital domain. The method is aimed at reducing the cost of test (CoT) for systems-on-chip (SoC) devices while taking advantage of digital resources already present in the SoC devices, and using low-cost digital testers, respectively. It is based on Walsh functions, the Fast Walsh Transformation (FWT) and a simple digital processing algorithm. Since both test signal generation and test response analysis are performed on-chip, it leads to an efficient and robust approach very suitable to built-in self-test (BIST) applications, too. Considerations for on-chip implementation are also addressed together with simulation and experimental results that validate the feasibility of the proposed approach.